Mahmoud A. Khalil

Orcid: 0009-0002-2168-0001

According to our database1, Mahmoud A. Khalil authored at least 6 papers between 2018 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
36.7 A 1.54pJ/b 64Gb/s 16-QAM Intradyne Coherent Optical Receiver in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024
7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Carrier-Phase-Recovery Loop for a 3.2pJ/b 24Gb/s QPSK Coherent Optical Receiver.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2018
Design Trade-offs in Buck Converters for Low-Energy Wireless Transceivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Low-ripple PFM Buck Converter Employing Background Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018


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