Mohamed Saad Aly
Orcid: 0009-0009-7046-9369
According to our database1,
Mohamed Saad Aly authored at least 6 papers
between 2025 and 2026.
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Bibliography
2026
IEEE J. Solid State Circuits, January, 2026
A 12-25GHz Ring-PLL Clock Generator Achieving 98fs Jitter and <-52dBc Spurs Using a 22fs Quadrupler and Sub-Sampling Error Extraction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 64-Gb/s QPSK Carrier-Phase-Recovery Loop with Wide IF Range Using Dual-Oscillator Frequency Translation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 14GHz 16-Phase Calibration-Free Fractional-N Ring-PLL with 118fs Jitter Using Phase- and Voltage-domain Quantization Error Cancellation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 4x4 MIMO Equalizer for Polarization Crosstalk Cancellation in 160 Gb/s DP-QPSK/16QAM Coherent Optical Receivers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
Proceedings of the IEEE International Solid-State Circuits Conference, 2025