Mohamed Badr Younis
Orcid: 0009-0008-7531-1360Affiliations:
- University of Illinois at Urbana-Champaign, Urbana, IL, USA
According to our database1,
Mohamed Badr Younis authored at least 16 papers
between 2022 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
An 8-ppm/°C 100-MHz RC Oscillator With Implicit Temperature Compensation and Resistor Aging Characterization.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2026
A Carrier Phase Recovery Loop for a 3.2-pJ/b, 24-Gb/s QPSK Coherent Optical Receiver.
IEEE J. Solid State Circuits, May, 2026
IEEE J. Solid State Circuits, January, 2026
A 12-25GHz Ring-PLL Clock Generator Achieving 98fs Jitter and <-52dBc Spurs Using a 22fs Quadrupler and Sub-Sampling Error Extraction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 64-Gb/s QPSK Carrier-Phase-Recovery Loop with Wide IF Range Using Dual-Oscillator Frequency Translation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 56 Gb/s/wire, 0.75 pJ/b Transceiver for Die-to-Die Interface Using Simultaneous Bi-Directional Signaling.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 14GHz 16-Phase Calibration-Free Fractional-N Ring-PLL with 118fs Jitter Using Phase- and Voltage-domain Quantization Error Cancellation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
Fractional-N PLL-Based Micro-Oven Control for Ultra-Stable MEMS Frequency References.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
A 4x4 MIMO Equalizer for Polarization Crosstalk Cancellation in 160 Gb/s DP-QPSK/16QAM Coherent Optical Receivers.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
CoRR, September, 2025
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
7.8 A 69.3fs Ring-Based Sampling-PLL Achieving 6.8GHz-14GHz and -54.4dBc Spurs Under 50mV Supply Noise.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator.
IEEE J. Solid State Circuits, March, 2023
A 5.2 Gb/s 3 mm Air-Gap 4.7 pJ/bit Capacitively-Coupled Transceiver for Giant Video Walls Enabled by a Dual-Edge Tracking Clock and Data Recovery Loop.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 20µs turn-on time, 24kHz resolution, 1.5-100MHz digitally programmable temperature-compensated clock generator with 7.5ppm/°C inaccuracy.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022