Pavan Kumar Hanumolu

Affiliations:
  • University of Illinois, Urbana-Champaign, IL, USA


According to our database1, Pavan Kumar Hanumolu authored at least 171 papers between 2003 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2021
A 91.15% Efficient 2.3-5-V Input 10-35-V Output Hybrid Boost Converter for LED-Driver Applications.
IEEE J. Solid State Circuits, 2021

New Associate Editor.
IEEE J. Solid State Circuits, 2021

A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling.
IEEE J. Solid State Circuits, 2021

A second-order temperature compensated 1μW/MHz 100MHz RC oscillator with ±140ppm inaccuracy from -40°C to 95°C.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

A 3.2GHz 405fsrms jitter -237.2dB-FoMJIT ring-based fractional-N synthesizer using two-step quantization noise cancellation and piecewise-linear nonlinearity correction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020

A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques.
IEEE J. Solid State Circuits, 2020

New Associate Editors.
IEEE J. Solid State Circuits, 2020

Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS.
IEEE J. Solid State Circuits, 2020

3.2 A 0.0088mm<sup>2</sup> Resistor-Based Temperature Sensor Achieving 92fJ·K<sup>2</sup> FoM in 65nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

3.5 A 34µW 32MHz RC Oscillator with ±530ppm Inaccuracy from -40°C to 85°C and 80ppm/V Supply Sensitivity Enabled by Pulse-Density Modulated Resistors.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A 91% efficient 30V hybrid boost-SC converter based backlight LED driver in 180nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A 6 $\mu$ W ±50 ppm/°C ±1500 ppm/V 1.5 MHz $RC$ Oscillator Using Self-Regulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Signal Processing Foundations for Time-Based Signal Representations: Neurobiological parallels to engineered systems designed for energy efficiency or hardware simplicity.
IEEE Signal Process. Mag., 2019

A 0.016 mm<sup>2</sup> 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS.
IEEE J. Solid State Circuits, 2019

A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection.
IEEE J. Solid State Circuits, 2019

Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers.
IEEE J. Solid State Circuits, 2019

A 15-Gb/s Sub-Baud-Rate Digital CDR.
IEEE J. Solid State Circuits, 2019

Message From the Incoming Editor-in-Chief.
IEEE J. Solid State Circuits, 2019

A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler.
IEEE J. Solid State Circuits, 2019

34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers.
IEEE J. Solid State Circuits, 2019

A 54MHz Crystal Oscillator With 30× 18.5 Start-Up Time Reduction Using 2-Step Injection in 65nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 5GHz 245fsrms 8mW Ring Oscillator-based Digital Frequency Synthesizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A Modulo-Based Architecture for Analog-to-Digital Conversion.
IEEE J. Sel. Top. Signal Process., 2018

A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects.
IEEE J. Solid State Circuits, 2018

A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes.
IEEE J. Solid State Circuits, 2018

Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers.
IEEE J. Solid State Circuits, 2018

A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier.
IEEE J. Solid State Circuits, 2018

A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation.
IEEE J. Solid State Circuits, 2018

A 12-Gb/s -16.8-dBm OMA Sensitivity 23-mW Optical Receiver in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters - An Alternative to Conventional Analog and Digital Controllers.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Session 25 overview: Clock generation for high-speed links: Wireline subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 5GHz 370fsrms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

A 15Gb/s 1.9pJ/bit sub-baud-rate digital CDR.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 0.0021 mm<sup>2</sup> 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017

A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017

A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver.
IEEE J. Solid State Circuits, 2017

F2: High-performance frequency generation for wireless and wireline systems.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

EE4: Semiconductor economics: How business decisions are engineered.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Understanding and Optimizing Power Consumption in Memory Networks.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 0.7V time-based inductor for fully integrated low bandwidth filter applications.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Time-based ΑΣADCs.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition.
IEEE J. Solid State Circuits, 2016

A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider.
IEEE J. Solid State Circuits, 2016

A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity.
IEEE J. Solid State Circuits, 2016

19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

F4: Emerging short-reach and high-density interconnect solutions for internet of everything.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications.
IEEE J. Solid State Circuits, 2015

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.
IEEE J. Solid State Circuits, 2015

A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator.
IEEE J. Solid State Circuits, 2015

High Frequency Buck Converter Design Using Time-Based Control Techniques.
IEEE J. Solid State Circuits, 2015

Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers.
IEEE J. Solid State Circuits, 2015

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC.
IEEE J. Solid State Circuits, 2015

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links.
IEEE J. Solid State Circuits, 2015

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links.
IEEE J. Solid State Circuits, 2015

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm<sup>2</sup> 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

10.7 A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

3.8 A 0.45-to-0.7V 1-to-6Gb/S 0.29-to-0.58pJ/b source-synchronous transceiver using automatic phase calibration in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Low dropout regulators.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS.
IEEE J. Solid State Circuits, 2014

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop.
IEEE J. Solid State Circuits, 2014

A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis.
IEEE J. Solid State Circuits, 2014

A Deterministic Digital Background Calibration Technique for VCO-Based ADCs.
IEEE J. Solid State Circuits, 2014

Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2014

A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques.
IEEE J. Solid State Circuits, 2014

A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links.
IEEE J. Solid State Circuits, 2014

A 75dB DR 50MHz BW 3<sup>rd</sup> order CT-ΔΣ modulator using VCO-based integrators.
Proceedings of the Symposium on VLSI Circuits, 2014

A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter.
Proceedings of the Symposium on VLSI Circuits, 2014

A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.
Proceedings of the Symposium on VLSI Circuits, 2014

A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW.
Proceedings of the Symposium on VLSI Circuits, 2014

A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC.
Proceedings of the Symposium on VLSI Circuits, 2014

8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A VCO-based current-to-digital converter for sensor applications.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW.
IEEE J. Solid State Circuits, 2013

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops.
IEEE J. Solid State Circuits, 2013

A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Rail-to-Rail Input Pipelined ADC Incorporating Multistage Signal Mapping.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer.
IEEE J. Solid State Circuits, 2012

Analog Filter Design Using Ring Oscillator Integrators.
IEEE J. Solid State Circuits, 2012

Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques.
Proceedings of the 25th International Conference on VLSI Design, 2012

A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control.
Proceedings of the Symposium on VLSI Circuits, 2012

A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity.
Proceedings of the Symposium on VLSI Circuits, 2012

A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 0.55V 61dB-SNR 67dB-SFDR 7MHz 4<sup>th</sup>-order Butterworth filter using ring-oscillator-based integrators in 90nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Calibration technique for SAR analog-to-digital converters.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Design Techniques for Wideband Discrete-Time Delta-Sigma ADCs With Extra Loop Delay.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Design-Oriented Analysis of Circuits With Equality Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking.
IEEE J. Solid State Circuits, 2011

A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery.
IEEE J. Solid State Circuits, 2011

A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique.
IEEE J. Solid State Circuits, 2011

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance.
IEEE J. Solid State Circuits, 2011

A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration.
IEEE J. Solid State Circuits, 2011

A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N control.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A high-PSR LDO using a feedforward supply-noise cancellation technique.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Digital clock and data recovery circuit design: Challenges and tradeoffs.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Area efficient phase calibration of a 1.6 GHz multiphase DLL.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Continuous-Time Input Pipeline ADCs.
IEEE J. Solid State Circuits, 2010

A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 1.2A 2MHz tri-mode Buck-Boost LED driver with feed-forward duty cycle correction.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A Digital PLL With a Stochastic Time-to-Digital Converter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Automated Design and Optimization of Low-Noise Oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers.
IEEE J. Solid State Circuits, 2009

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback.
IEEE J. Solid State Circuits, 2009

A 10 MS/s 11-bit 0.19 mm<sup>2</sup> Algorithmic ADC With Improved Clocking Scheme.
IEEE J. Solid State Circuits, 2009

Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture.
IEEE J. Solid State Circuits, 2009

An 8×5 Gb/s Parallel Receiver With Collaborative Timing Recovery.
IEEE J. Solid State Circuits, 2009

A multiplexer-based digital passive linear counter (PLINCO).
Proceedings of the 16th IEEE International Conference on Electronics, 2009

An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

Over-sampled data converters.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A continuous-time input pipeline ADC with inherent anti-alias filtering.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Sensitivity Analysis for Oscillators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC.
IEEE J. Solid State Circuits, 2008

A Wide-Tracking Range Clock and Data Recovery Circuit.
IEEE J. Solid State Circuits, 2008

A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter.
IEEE J. Solid State Circuits, 2008

An 8×3.2Gb/s Parallel Receiver with Collaborative Timing Recovery.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Supply-noise mitigation techniques in phase-locked loops.
Proceedings of the ESSCIRC 2008, 2008

Periodic Steady-State Analysis Augmented with Design Equality Constraints.
Proceedings of the Design, Automation and Test in Europe, 2008

Noise tolerant oscillator design using perturbation projection vector analysis.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 1V downconversion filter using duty-cycle controlled bandwidth tuning.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A continuous-time input pipeline ADC.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters.
IEEE J. Solid State Circuits, 2007

Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Digitally-Enhanced Phase-Locking Circuits.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 3.2Gb/s Oversampling CDR with Improved Jitter Tolerance.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

A 1V 10b 30MSPS Switched-RC Pipelined ADC.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning.
IEEE J. Solid State Circuits, 2006

A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Constant transconductance bias circuit with an on-chip resistor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 0.6V Highly Linear Switched-R-MOSFET-C Filter.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 1.6Gbps Digital Clock and Data Recovery Circuit.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A low spur fractional-N frequency synthesizer architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Analysis of charge-pump phase-locked loops.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Jitter in high-speed serial and parallel links.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 0.8V accurately-tuned continuous-time filter.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Analysis of PLL clock jitter in high-speed serial links.
IEEE Trans. Circuits Syst. II Express Briefs, 2003


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