Mahyar Emami

Orcid: 0000-0002-5654-8804

According to our database1, Mahyar Emami authored at least 9 papers between 2020 and 2025.

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Bibliography

2025
Parendi: Thousand-Way Parallel RTL Simulation.
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

2024
Performance Interfaces for Hardware Accelerators.
Proceedings of the 18th USENIX Symposium on Operating Systems Design and Implementation, 2024

A 475 MHz Manycore FPGA Accelerator for RTL Simulation.
Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

2023
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
StreamBlocks: A compiler for heterogeneous dataflow computing (technical report).
CoRR, 2021

Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

2020
Advanced Dataflow Programming using Actor Machines for High-Level Synthesis.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020


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