Endri Bezati
Orcid: 0000-0003-3446-9838
According to our database1,
Endri Bezati
authored at least 49 papers
between 2010 and 2022.
Collaborative distances:
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Bibliography
2022
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022
2021
CoRR, 2021
Generating hardware and software for RISC-V cores generated with Rocket Chip generator.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
2020
J. Signal Process. Syst., 2020
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
2019
Proceedings of the 7th International Conference on Model-Driven Engineering and Software Development, 2019
Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism.
Proceedings of the Computational Science - ICCS 2019, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
2018
High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs.
IEEE Trans. Multi Scale Comput. Syst., 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
2017
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms.
Proceedings of the 25th European Signal Processing Conference, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
Execution trace graph based interface synthesis of signal processing dataflow programs for heterogeneous MPSoCs.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
J. Signal Process. Syst., 2016
Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques - Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies.
J. Signal Process. Syst., 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
Proceedings of the International Conference on Computational Science 2016, 2016
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Proceedings of the International Conference on Computational Science, 2015
2014
High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms.
J. Real Time Image Process., 2014
Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
TURNUS: An open-source design space exploration framework for dynamic stream programs.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
Signal Process. Image Commun., 2013
Partitioning and optimization of high level stream applications for multi clock domain architectures.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013
Design space exploration and implementation of RVC-CAL applications using the TURNUS framework.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
J. Electr. Comput. Eng., 2012
Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
2011
Hardware/software co-design of dataflow programs for reconfigurable hardware and multi-core platforms.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010