Mallika Rathore

Orcid: 0000-0002-3829-3887

According to our database1, Mallika Rathore authored at least 4 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Precision and Performance-Aware Voltage Scaling in DNN Accelerators.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2020
Error Probability Models for Voltage-Scaled Multiply-Accumulate Units.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2018
Error Probability Models to Facilitate Approximate Computing in TFET based Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2015
A Novel Static D-Flip-Flop Topology for Low Swing Clocking.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015


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