Emre Salman

Orcid: 0000-0001-6538-6803

According to our database1, Emre Salman authored at least 86 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
A New Dataflow Implementation to Improve Energy Efficiency of Monolithic 3D Systolic Arrays.
CoRR, 2024

2023
TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated Systems.
Sensors, February, 2023

SEAL-RF: Secure Adiabatic Logic for Wirelessly Powered IoT Devices.
IEEE Internet Things J., January, 2023

Thermal Integrity of ReRAM-based Near-Memory Computing in 3D Integrated DNN Accelerators.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Information-Theoretic Perspective to Thermal Covert Channels.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Precision and Performance-Aware Voltage Scaling in DNN Accelerators.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Power Transfer Optimization for Triboelectric Nanogenerators.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

2022
High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Temperature-Aware Monolithic 3D DNN Accelerators for Biomedical Applications.
CoRR, 2022

Wireless Power Transfer for Smart Knee Implants.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Session details: Session 2B: Computer-Aided Design (CAD).
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
PhaseCamouflage: Leveraging Adiabatic Operation to Thwart Reverse Engineering.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Monolithic 3D Integrated Circuits: Recent Trends and Future Prospects.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Towards Enhancing Power-Analysis Attack Resilience for Logic Locking Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

EQUAL: Efficient QUasi Adiabatic Logic for Enhanced Side-Channel Resistance.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Assessing Correlation Power Analysis (CPA) Attack Resilience of Transistor-Level Logic Locking.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Error Probability Models for Voltage-Scaled Multiply-Accumulate Units.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Establishing a Covert Communication Channel in RF and mm-Wave Circuits.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

High Efficiency Fully Integrated On-Chip Regulator for Wide-Range Output Current.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Special Session: Adiabatic Circuits for Energy-Efficient and Secure IoT Systems.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
AC Computing Methodology for RF-Powered IoT Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2019

SLECTS: Slew-Driven Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Frontend Electronic System for Triboelectric Harvester in a Smart Knee Implant.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Power and Data Integrity in Monolithic 3D Integrated SIMON Core.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Signal Shaping at Interface of Wireless Power Harvesting and AC Computational Logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Low Voltage Clock Tree Synthesis with Local Gate Clusters.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

An Overview of Thermal Challenges and Opportunities for Monolithic 3D ICs.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Mono3D: Open Source Cell Library for Monolithic 3-D Integrated Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Ultra Low Power SIMON Core for Lightweight Encryption.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Error Probability Models to Facilitate Approximate Computing in TFET based Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Leveraging RF Power for Intelligent Tag Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
Closed-Form Expressions for I/O Simultaneous Switching Noise Revisited.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Package-embedded spiral inductor characterization with application to switching buck converters.
Microelectron. J., 2017

Perspective Paper - Can AC Computing Be an Alternative for Wirelessly Powered IoT Devices?
IEEE Embed. Syst. Lett., 2017

Open source cell library Mono3D to develop large-scale monolithic 3D integrated circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

In-package spiral inductor characterization for high efficiency buck converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Energy efficient AC computing methodology for wirelessly powered IoT devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Routing Congestion Aware Cell Library Development for Monolithic 3D ICs.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Design Methodology for Voltage-Scaled Clock Distribution Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A new circuit design framework for IoT devices: Charge-recycling with wireless power harvesting.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

On-chip hybrid regulator topology for portable SoCs with near-threshold operation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Exploiting useful skew in gated low voltage clock trees.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Transistor-level camouflaged logic locking method for monolithic 3D IC security.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Hardware Security Threats and Potential Countermeasures in Emerging 3D ICs.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Figures-of-Merit to Evaluate the Significance of Switching Noise in Analog Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Quantifying the effect of local interconnects on on-chip power distribution.
Microelectron. J., 2015

FinFET-Based Low-Swing Clocking.
ACM J. Emerg. Technol. Comput. Syst., 2015

Resource allocation methodology for through silicon vias and sleep transistors in 3D ICs.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Enhancing system-wide power integrity in 3D ICs with power gating.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Enhanced level shifter for multi-voltage operation.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Low swing TSV signaling using novel level shifters with single supply voltage.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A wirelessly powered system with charge recovery logic.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A Novel Static D-Flip-Flop Topology for Low Swing Clocking.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs.
Integr., 2014

High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2013
Power gating topologies in TSV based 3D integrated circuits.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Efficient characterization of TSV-to-transistor noise coupling in 3D ICs.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Effect of TSV fabrication technology on power distribution in 3D ICs.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012
Utilizing interdependent timing constraints to enhance robustness in synchronous circuits.
Microelectron. J., 2012

Power Distribution in TSV-Based 3-D Processor-Memory Stacks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

Design space exploration for robust power delivery in TSV based 3-D systems-on-chip.
Proceedings of the IEEE 25th International SOC Conference, 2012

Methodology to determine dominant noise source in a system-on-chip based implantable device.
Proceedings of the IEEE 25th International SOC Conference, 2012

2011
Shielding Methodologies in the Presence of Power/Ground Noise.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Noise coupling due to through silicon vias (TSVs) in 3-D integrated circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Compact substrate models for efficient noise coupling and signal isolation analysis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Methodology to achieve higher tolerance to delay variations in synchronous circuits.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Contact merging algorithm for efficient substrate noise analysis in large scale circuits.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
Pseudo-random clocking to enhance signal integrity.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Input port reduction for efficient substrate extraction in large scale IC's.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Equivalent rise time for resonance in power/ground noise estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Substrate Noise Reduction Based On Noise Aware Cell Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Substrate and Ground Noise Interactions in Mixed-Signal Circuits.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006


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