Weicheng Liu

Orcid: 0000-0001-8779-2079

According to our database1, Weicheng Liu authored at least 21 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
High-Efficiency Time-Division Multiplexing Modulation Technology for Modular Multiactive Bridge Converters.
IEEE Trans. Ind. Electron., June, 2024

Real-Time Digital Mapped Method for Sensorless Multitimescale Operation Condition Monitoring of Power Electronics Systems.
IEEE Trans. Ind. Electron., April, 2024

A Semi-Implicit Parallel Leapfrog Solver With Half-Step Sampling Technique for FPGA-Based Real-Time HIL Simulation of Power Converters.
IEEE Trans. Ind. Electron., March, 2024

Wireless Universal Adversarial Attack and Defense for Deep Learning-Based Modulation Classification.
IEEE Commun. Lett., March, 2024

2023
Investigation of the Causal Relationship Between Alcohol Consumption and COVID-19: A Two-Sample Mendelian Randomization Study.
Int. J. Comput. Intell. Syst., December, 2023

Hidden Backdoor Attack Against Deep Learning-Based Wireless Signal Modulation Classifiers.
IEEE Trans. Veh. Technol., September, 2023

An Event-Based Synchronization Framework for Controller Hardware-in-the-loop Simulation of Electric Railway Power Electronics Systems.
CoRR, 2023

Accurate Time-segmented Loss Model for SiC MOSFETs in Electro-thermal Multi-Rate Simulation.
CoRR, 2023

FPGA-Based Implicit-Explicit Real-time Simulation Solver for Railway Wireless Power Transfer with Nonlinear Magnetic Coupling Components.
CoRR, 2023

2022
Validation of Four Satellite-Derived Soil Moisture Products Using Ground-Based In Situ Observations over Northern China.
Remote. Sens., 2022

GAN Against Adversarial Attacks in Radio Signal Classification.
IEEE Commun. Lett., 2022

Generative Design of XingT, A Human-sized Heavy-duty Bipedal Robot.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2022

2019
SLECTS: Slew-Driven Clock Tree Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Low Voltage Clock Tree Synthesis with Local Gate Clusters.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2016
Design Methodology for Voltage-Scaled Clock Distribution Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Exploiting useful skew in gated low voltage clock trees.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Torchless: Asymmetry in a Shared Screen Dungeon Crawler.
Proceedings of the 2016 Annual Symposium on Computer-Human Interaction in Play, 2016

2015
Enhanced level shifter for multi-voltage operation.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A Novel Static D-Flip-Flop Topology for Low Swing Clocking.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
An area-efficient LDMOS-SCR ESD protection device for the I/O of power IC application.
Microelectron. Reliab., 2014


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