Mamata Dalui

Biomed. Signal Process. Control., February, 2024

2023

Design, threat analysis and countermeasures for cache replacement policy-affecting Hardware Trojans in the context of a many-core system.

[BibT_eX]

[DOI]

Boppudi Avinash

Microelectron. J., December, 2023

Smartphone-based non-invasive haemoglobin level estimation by analyzing nail pallor.

[BibT_eX]

[DOI]

Bibhash Sen

Suchismita Roy

Anupam Basu

Biomed. Signal Process. Control., August, 2023

Non-invasive anaemia detection by examining palm pallor: A smartphone-based approach.

[BibT_eX]

[DOI]

Bibhash Sen

Suchismita Roy

Anupam Basu

Biomed. Signal Process. Control., 2023

Real time detection of cognitive load using fNIRS: A deep learning approach.

[BibT_eX]

[DOI]

Subashis Karmakar

Supreeti Kamilya

Prasenjit Dey

Parag K. Guhathakurta

Biomed. Signal Process. Control., 2023

2022

Characterization of Single Length Cycle Two-Attractor Cellular Automata Using Next-State Rule Minterm Transition Diagram.

[BibT_eX]

[DOI]

Complex Syst., 2022

Non-invasive Haemoglobin Prediction Using Nail Color Features: An Approach of Dimensionality Reduction.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Computing Theories and Application, 2022

Non-invasive Haemoglobin Estimation Using Different Colour and Texture Features of Palm.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision and Image Processing - 7th International Conference, 2022

Synthesis of Single Length Cycle Two Attractor CA Using NSRT Diagram.

[BibT_eX]

[DOI]

Proceedings of First Asian Symposium on Cellular Automata Technology, 2022

2021

Synthesis of Scalable Single Length Cycle, Single Attractor Cellular Automata in Linear Time.

[BibT_eX]

[DOI]

Complex Syst., 2021

COVID-19 Detection on Chest X-Ray and CT Scan Images Using Multi-image Augmented Deep Learning Model.

[BibT_eX]

[DOI]

Kiran Purohit

Proceedings of the Seventh International Conference on Mathematics and Computing, 2021

2020

CA-Based Detection of Coherence Exploiting Hardware Trojans.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2020

Design, Threat Analysis and Countermeasure for a Cache Performance Affecting Hardware Trojan.

[BibT_eX]

[DOI]

Boppudi Avinash

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019

Cellular Automata Based Test Design for Coherence Verification in 3D Caches.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

Cellular Automata Based Solution for Detecting Hardware Trojan in CMPs.

[BibT_eX]

[DOI]

Proceedings of the Recent Advances in Intelligent Information Systems and Applied Mathematics, 2019

2018

Design of a Reliable Cache System for Heterogeneous CMPs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2018

Evaluation and Detection of Hardware Trojan for Real-Time Many-Core Systems.

[BibT_eX]

[DOI]

Jaswanth Sai Sattenapalli

Arka Roy

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

A Cellular Automata Based BIST for Detecting NPSFs in High Speed Memories.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Software and Computer Applications, 2018

Evaluation of Misspeculation Impact on Chip-Multiprocessors Power Overhead.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Software and Computer Applications, 2018

2017

A cellular automata based self-correcting protocol processor for scalable CMPs.

[BibT_eX]

[DOI]

Microelectron. J., 2017

Design of Coherence Verification Unit for Heterogeneous CMPs Integrating Update and Invalidate Protocols.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Pre-bond Testing of TSVs in 3D IC Using Segmented Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the Information Technology and Applied Mathematics - ICITAM 2017, Haldia, Purba Medinipur, West Bengal, India, October 30, 2017

2016

A Cache System Design for CMPs with Built-In Coherence Verification.

[BibT_eX]

[DOI]

VLSI Design, 2016

A cellular automata based highly accurate memory test hardware realizing March C<sup>-</sup>.

[BibT_eX]

[DOI]

Saha Mousumi

Microelectron. J., 2016

Design of coherence verification unit for CMPs realizing dragon protocol.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

MASI: An eviction aware cache coherence protocol for CMPs.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

CA based protocol processor for heterogeneous CMPs.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

2015

Design of coherence verification unit for heterogeneous CMPs.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014

CA Based Scalable Protocol Processor for Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2013

Directory based cache coherence verification logic in CMPs cache system.

[BibT_eX]

[DOI]

Keshav Gupta

Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

Design of directory based cache coherence protocol verification logic in CMPs around TACA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2013

2012

An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol.

[BibT_eX]

[DOI]

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

A Test Design for Quick Determination of Incoherency in Chip Multiprocessors' Cache Realizing MOESI Protocol.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Electronic System Design, 2012

2011

An Efficient Test Design for Verification of Cache Coherence in CMPs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Ninth International Conference on Dependable, 2011

2010

CA based quick consensus in distributed system through network partitioning.

[BibT_eX]

[DOI]

Suhrid Bakshi

Proceedings of the IEEE International Conference on Systems, 2010

SSMCA: CA based Segmented Sensor Network Management scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Systems, 2010

Introducing universal QCA logic gate for synthesizing symmetric functions with minimum wire-crossings.

[BibT_eX]

[DOI]

Bibhash Sen

Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26, 2010

Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Characterization of CA Rules for SACA Targeting Detection of Faulty Nodes in WSN.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2010

2009

Quick Consensus Through Early Disposal of Faulty Processes.

[BibT_eX]

[DOI]

Biplab Kumar Sikdar