Suchismita Roy

According to our database, Suchismita Roy authored at least 37 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity.

Anindan Mondal, Debasish Kalita, Archisman Ghosh, Suchismita Roy, Bibhash Sen

ACM J. Emerg. Technol. Comput. Syst., October, 2023

Smartphone-based non-invasive haemoglobin level estimation by analyzing nail pallor.

Sunanda Das, Abhishek Kesarwani, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu

Biomed. Signal Process. Control., August, 2023

Hardware Trojan Detection using Transition Probability with Minimal Test Vectors.

Anindan Mondal, Shubrojyoti Karmakar, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen, Anupam Chattopadhyay

ACM Trans. Embed. Comput. Syst., 2023

Non-invasive anaemia detection by examining palm pallor: A smartphone-based approach.

Abhishek Kesarwani, Sunanda Das, Mamata Dalui, Dakshina Ranjan Kisku, Bibhash Sen, Suchismita Roy, Anupam Basu

Biomed. Signal Process. Control., 2023

2022

Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SAT.

Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee

J. Circuits Syst. Comput., 2022

Power aware floorplanning in multiple supply voltage domain.

Suchandra Banerjee, Suchismita Roy

Int. J. Circuit Theory Appl., 2022

2021

Thermal-Driven Floorplanning for Fixed Outline Layouts.

Suchandra Banerjee, Suchismita Roy

J. Circuits Syst. Comput., 2021

Hardware Trojan Free Netlist Identification: A Clustering Approach.

Anindan Mondal, Rajesh Kumar Biswal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen

J. Electron. Test., 2021

PUF based Lightweight Authentication and Key Exchange Protocol for IoT.

Sourav Roy, Dipnarayan Das, Anindan Mondal, Mahabub Hasan Mahalat, Suchismita Roy, Bibhash Sen

Proceedings of the 18th International Conference on Security and Cryptography, 2021

2020

Corrigendum to: "Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares" [Theor. Comput. Sci. 769 (2019) 63-74].

Sanjib Sadhu, Xiaozhou He, Sasanka Roy, Subhas C. Nandy, Suchismita Roy

Theor. Comput. Sci., 2020

Rectilinear Steiner Tree Construction Techniques Using PB-SAT-Based Methodology.

Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee

J. Circuits Syst. Comput., 2020

Efficient Algorithm for Computing the Triangle Maximizing the Length of Its Smallest Side Inside a Convex Polygon.

Sanjib Sadhu, Sasanka Roy, Soumen Nandi, Subhas C. Nandy, Suchismita Roy

Int. J. Found. Comput. Sci., 2020

2019

Application-Dependent Testing of FPGA Interconnect Network.

Shukla Banik, Suchismita Roy, Bibhash Sen

IEEE Trans. Very Large Scale Integr. Syst., 2019

Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares.

Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy

Theor. Comput. Sci., 2019

A SAT-Based Methodology for Effective Clock Gating for Power Minimization.

Khushbu Chandrakar, Suchismita Roy

J. Circuits Syst. Comput., 2019

An Integrated Framework for Application Independent Testing of FPGA Interconnect.

Shukla Banik, Suchismita Roy, Bibhash Sen

J. Electron. Test., 2019

Corrigendum to: "Linear time algorithm to cover and hit a set of line segments optimally by two axis-parallel squares", Theoretical Computer Science 769 (2019) 63-74.

Sanjib Sadhu, Xiaozhou He, Sasanka Roy, Subhas C. Nandy, Suchismita Roy

CoRR, 2019

Test Configuration Generation for Different FPGA Architectures for Application Independent Testing.

Shukla Banik, Suchismita Roy, Bibhash Sen

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A Novel Test Vector Generation Method for Hardware Trojan Detection.

Anindan Mondal, Mahabub Hasan Mahalat, Suraj Mandal, Suchismita Roy, Bibhash Sen

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018

Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption.

Khushbu Chandrakar, Sudeshna Kundu, Suchismita Roy

J. Low Power Electron., 2018

XOR based Methodology to Detect Hardware Trojan utilizing the Transition Probability.

Anindan Mondal, Mahabub Hasan Mahalat, Anudeep Reddy Medapati, Suchismita Roy, Bibhash Sen

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2017

Via-Aware Dogleg Routing Using Boolean Satisfiability.

Shyamapada Mukherjee, Suchismita Roy

J. Circuits Syst. Comput., 2017

K-nearest neighbour (KNN) approach using SAT based technique for rectilinear steiner tree construction.

Sudeshna Kundu, Suchismita Roy, Shyamapada Mukherjee

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Computing the Triangle Maximizing the Length of Its Smallest Side Inside a Convex Polygon.

Sanjib Sadhu, Sasanka Roy, Soumen Nandi, Subhas C. Nandy, Suchismita Roy

Proceedings of the Computational Science and Its Applications - ICCSA 2017, 2017

Optimal Covering and Hitting of Line Segments by Two Axis-Parallel Squares.

Sanjib Sadhu, Sasanka Roy, Subhas C. Nandy, Suchismita Roy

Proceedings of the Computing and Combinatorics - 23rd International Conference, 2017

2016

Nearly-2-SAT Solutions for Segmented-Channel Routing.

Shyamapada Mukherjee, Suchismita Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Satisfiability modulo theory based methodology for floorplanning in VLSI circuits.

Suchandra Banerjee, Anand Ratna, Suchismita Roy

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

2015

SAT based solutions for detailed routing of island style FPGA architectures.

Shyamapada Mukherjee, Suchismita Roy

Microelectron. J., 2015

Multi terminal net routing for island style FPGAs using nearly-2-SAT computation.

Shyamapada Mukherjee, Suchismita Roy

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2013

Congestion Balancing Global Router.

Shyamapada Mukherjee, Jibesh Patra, Suchismita Roy

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

SAT based low power binding to reduce switching activity.

Khushbu Chandrakar, Suchismita Roy

Proceedings of the Sixth International Conference on Contemporary Computing, 2013

2012

SAT based timing analysis for fixed and rise/fall gate delay models.

Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta

Integr., 2012

2010

Bounded delay timing analysis and power estimation using SAT.

Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta

Microelectron. J., 2010

2008

Satisfiability Models for Maximum Transition Power.

Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta

IEEE Trans. Very Large Scale Integr. Syst., 2008

2007

Event propagation for accurate circuit delay calculation using SAT.

Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta

ACM Trans. Design Autom. Electr. Syst., 2007

Bounded Delay Timing Analysis Using Boolean Satisfiability.

Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2005

SAT based solutions for consistency problems in formal property specifications for open systems.

Suchismita Roy, Sayantan Das, Prasenjit Basu, Pallab Dasgupta, Partha Pratim Chakrabarti

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005