Biplab K. Sikdar

Rajat Subhra Chakraborty

Integr., March, 2024

LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore.

[BibT_eX]

[DOI]

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictor.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2023

2022

Cellular automata based multi-bit stuck-at fault diagnosis for resistive memory.

[BibT_eX]

[DOI]

Sutapa Sarkar

Frontiers Inf. Technol. Electron. Eng., 2022

Performance Analysis of Regular Clocking Based Quantum-Dot Cellular Automata Logic Circuit: Fault Tolerant Approach.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2022

Identification of Periodic Boundary SACA Rules Exploring NSRT Diagram.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2022

2021

A trojan framework in AES core to evade state-of-the-art HT detection schemes.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Simulation of Non-uniform Cellular Automata by Classical Cellular Automata and Its Application in Embedded Systems.

[BibT_eX]

[DOI]

Supreeti Kamilya

J. Cell. Autom., 2021

Synthesis of Scalable Single Length Cycle, Single Attractor Cellular Automata in Linear Time.

[BibT_eX]

[DOI]

Complex Syst., 2021

2020

Modeling Remapping Based Fault Tolerance Techniques for Chip Multiprocessor Cache with Design Space Exploration.

[BibT_eX]

[DOI]

J. Electron. Test., 2020

Evaluation of Face Recognition Schemes for Low-computation IoT System Design.

[BibT_eX]

[DOI]

Jayanta Paul

Rajat Subhra Bhowmick

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Exploring Hard to Detect Sequential Hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019

Cellular Automata Based Test Design for Coherence Verification in 3D Caches.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

SACAs: (Non-uniform) Cellular Automata that Converge to a Single Fixed Point.

[BibT_eX]

[DOI]

J. Cell. Autom., 2019

Effect of Trojans on Write Data Access in Memory.

[BibT_eX]

[DOI]

Nilanjana Das

Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019

Soft Error Resilience in Chip Multiprocessor Cache using a Markov Model Based Re-usability Predictor.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Latency Aware Fault Tolerant Cache in Multicore Using Dynamic Remapping Clusters.

[BibT_eX]

[DOI]

Brototi Mondal

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

Design of a Reliable Cache System for Heterogeneous CMPs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2018

Modeling & Analysis of Redundancy Based Fault Tolerance for Permanent Faults in Chip Multiprocessor Cache.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Hard to Detect Combinational Hardware Trojans.

[BibT_eX]

[DOI]

Nilanjana Das

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

Stuck-At 0/1 Trojans on Return Address Stack.

[BibT_eX]

[DOI]

Nilanjana Das

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

ReMiT: Redundancy Migration for Latency Aware Fault Tolerant Cache Design in Multicore.

[BibT_eX]

[DOI]

Brototi Mondal

Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

Evaluation of Misspeculation Impact on Chip-Multiprocessors Power Overhead.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Software and Computer Applications, 2018

2017

Design of Testable Adder in Quantum-dot Cellular Automata with Fault Secure Logic.

[BibT_eX]

[DOI]

Microelectron. J., 2017

A cellular automata based self-correcting protocol processor for scalable CMPs.

[BibT_eX]

[DOI]

Microelectron. J., 2017

Evaluating impact on CMPs' power for design inaccuracy diagnosis.

[BibT_eX]

[DOI]

Int. J. Comput. Appl. Technol., 2017

Optimal synthesis of QCA logic circuit eliminating wire-crossings.

[BibT_eX]

[DOI]

Rajdeep Kumar Nath

IET Circuits Devices Syst., 2017

Design of Coherence Verification Unit for Heterogeneous CMPs Integrating Update and Invalidate Protocols.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

CIFR: A complete in-place fault remapping strategy for CMP cache using dynamic reuse distance.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Multi-bit fault tolerant design for resistive memories through dynamic partitioning.

[BibT_eX]

[DOI]

Sutapa Sarkar

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Periodic boundary cellular automata based test structure for memory.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2016

A Cache System Design for CMPs with Built-In Coherence Verification.

[BibT_eX]

[DOI]

VLSI Design, 2016

On the reliability of majority logic structure in quantum-dot cellular automata.

[BibT_eX]

[DOI]

Microelectron. J., 2016

A cellular automata based highly accurate memory test hardware realizing March C-.

[BibT_eX]

[DOI]

Microelectron. J., 2016

Towards Designing Reliable Universal QCA Logic in the Presence of Cell Deposition Defect.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Design of coherence verification unit for CMPs realizing dragon protocol.

[BibT_eX]

[DOI]

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Cellular automata based fault tolerant resistive memory design.

[BibT_eX]

[DOI]

Sutapa Sarkar

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Design of low power 5-input majority voter in quantum-dot cellular automata with effective error resilience.

[BibT_eX]

[DOI]

Mrinal Goswami

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Design of CA based scheme for evenhanded data migration in CMPs.

[BibT_eX]

[DOI]

Supreeti Kamilya

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

MASI: An eviction aware cache coherence protocol for CMPs.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

CA based protocol processor for heterogeneous CMPs.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

2015

Towards the hierarchical design of multilayer QCA logic circuit.

[BibT_eX]

[DOI]

J. Comput. Sci., 2015

Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2015

Fault masking in Quantum-dot cellular automata using prohibitive logic circuit.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

A fault tolerant test hardware for L1 cache module in tile CMPs architecture.

[BibT_eX]

[DOI]

Navneet Kumar Gautam

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Design of coherence verification unit for heterogeneous CMPs.

[BibT_eX]

[DOI]

Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

A Cellular Automata Based Fault Tolerant Approach in Designing Test Hardware for L1 Cache Module.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing.

[BibT_eX]

[DOI]

Manojit Dutta

Microelectron. J., 2014

Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability.

[BibT_eX]

[DOI]

Microelectron. J., 2014

Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2014

Design of Fault Tolerant Universal Logic in QCA.

[BibT_eX]

[DOI]

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

CA Based Scalable Protocol Processor for Chip Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2013

Analysis and synthesis of nonlinear reversible cellular automata in linear time.

[BibT_eX]

[DOI]

CoRR, 2013

Design of Sequential Circuits in Multilayer QCA Structure.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Design of an Efficient Scheme for Data Migration in Chip-Multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Directory based cache coherence verification logic in CMPs cache system.

[BibT_eX]

[DOI]

Keshav Gupta

Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

A cellular automata based design of self testable hardware for March C-.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2013

Design of directory based cache coherence protocol verification logic in CMPs around TACA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2013

2012

Characterization of Nonlinear Cellular Automata Having Only Single Length Cycle Attractors.

[BibT_eX]

[DOI]

Nazma Naskar

J. Cell. Autom., 2012

Rule Vector Graph (RVG) To Design Linear Time Algorithm for Identifying the Invertibility of Periodic-Boundary Three Neighborhood Cellular Automata.

[BibT_eX]

[DOI]

Soumyabrata Ghosh

J. Cell. Autom., 2012

An Efficient Multiplexer in Quantum-dot Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol.

[BibT_eX]

[DOI]

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Design of Fault Tolerant Reversible Arithmetic Logic Unit in QCA.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Electronic System Design, 2012

High Speed Hardware for March C¯.

[BibT_eX]

[DOI]

Souvik Das

Proceedings of the International Symposium on Electronic System Design, 2012

A Test Design for Quick Determination of Incoherency in Chip Multiprocessors' Cache Realizing MOESI Protocol.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Electronic System Design, 2012

A Cellular Automata Based Scheme for Energy Efficient Fault Diagnosis in WSN.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2012

Synthesis of Reversible Asynchronous Cellular Automata for Pattern Generation with Specific Hamming Distance.

[BibT_eX]

[DOI]

Anindita Sarkar

Proceedings of the Cellular Automata, 2012

Counting Cycles in Reversible Cellular Automata.

[BibT_eX]

[DOI]

Avik Chakraborty

Proceedings of the Cellular Automata, 2012

2011

On Invertible Three Neighborhood Null-Boundary Uniform Cellular Automata.

[BibT_eX]

[DOI]

Soumyabrata Ghosh

Complex Syst., 2011

A cellular automata based scheme for diagnosis of faulty nodes in WSN.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Systems, 2011

Synthesis of Reversible Universal Logic around QCA with Online Testability.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Electronic System Design, 2011

Impact of Inaccurate Design of Branch Predictors on Processors' Power Consumption.

[BibT_eX]

[DOI]

Proceedings of the IEEE Ninth International Conference on Dependable, 2011

An Efficient Test Design for Verification of Cache Coherence in CMPs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Ninth International Conference on Dependable, 2011

Exploring Impact of Faults on Branch Predictors' Power for Diagnosis of Faulty Module.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

DFDNM: A Distributed Fault Detection and Node Management Scheme for Wireless Sensor Network.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computing and Communications, 2011

2010

A Scalable Test Structure for Multicore Chip.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

CA based quick consensus in distributed system through network partitioning.

[BibT_eX]

[DOI]

Suhrid Bakshi

Proceedings of the IEEE International Conference on Systems, 2010

SSMCA: CA based Segmented Sensor Network Management scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Systems, 2010

Introducing universal QCA logic gate for synthesizing symmetric functions with minimum wire-crossings.

[BibT_eX]

[DOI]

Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26, 2010

Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Programmable Cellular Automata (PCA) Based Advanced Encryption Standard (AES) Hardware Architecture.

[BibT_eX]

[DOI]

Soumyabrata Ghosh

Proceedings of the Cellular Automata, 2010

Characterization of CA Rules for SACA Targeting Detection of Faulty Nodes in WSN.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2010

2009

Characterization of 1-d Periodic Boundary Reversible CA.

[BibT_eX]

[DOI]

Proceedings of the 15th International Workshop on Cellular Automata and Discrete Complex Systems, 2009

Characterization of Single Cycle CA and its Application in Pattern Classification.

[BibT_eX]

[DOI]

Proceedings of the 15th International Workshop on Cellular Automata and Discrete Complex Systems, 2009

Quick Consensus Through Early Disposal of Faulty Processes.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Systems, 2009

A Cellular Automata Based Model for Traffic in Congested City.

[BibT_eX]

[DOI]

Meghnath Saha

Proceedings of the IEEE International Conference on Systems, 2009

Cost Optimal Design of 3-D Steel Building Frames using CA-LFSR.

[BibT_eX]

[DOI]

Proceedings of the World Congress on Nature & Biologically Inspired Computing, 2009

Modeling Single Length Cycle Nonlinear Cellular Automata for Pattern Recognition.

[BibT_eX]

[DOI]

Proceedings of the World Congress on Nature & Biologically Inspired Computing, 2009

CA Rules Identification for Efficient Design of Pattern Classifier.

[BibT_eX]

Proceedings of the 2009 International Conference on Scientific Computing, 2009

CA Based Built-In Self-Test Structure for SoC.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Cellular Automata Based Design of Cost Optimal Steel Building Frames.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2008

Exploring Cycle Structures of Additive Cellular Automata.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2008

Exploring CAState Space to Synthesize Cellular Automata with Specified Attractor Set.

[BibT_eX]

[DOI]

Chandrama Shaw

Proceedings of the Cellular Automata, 2008

Characterization of Non-reachable States in Irreversible CAState Space.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2008

2007

Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Cellular Automata Model for Cost Optimal Design of Steel Building Frames.

[BibT_eX]

Proceedings of the 3rd Indian International Conference on Artificial Intelligence, 2007

CA Based Data Servicing In Cellular Mobile Network.

[BibT_eX]

DasBit Sipra

Proceedings of the 2007 International Conference on Wireless Networks, 2007

2006

An Energy Effilcient Monitoring of Ad-Hoc Sensor Network with Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Systems, 2006

Study of N-Detectability in QCA Designs.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

Cellular Automata Based Encoding Technique for Wavelet Transformed Data Targeting Still Image Compression.

[BibT_eX]

[DOI]

Chandrama Shaw

Proceedings of the Cellular Automata, 2006

Classification of CA Rules Targeting Synthesis of Reversible Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2006

2005

Fault diagnosis of VLSI circuits with cellular automata based pattern classifier.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area.

[BibT_eX]

[DOI]

Debesh K. Das

J. Electron. Test., 2005

Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time.

[BibT_eX]

[DOI]

Anirban Kundu

J. Electron. Test., 2005

Cellular Automata Based Test Structures with Logic Folding.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Non-linear cellular automata based design of query processor for mobile network.

[BibT_eX]

[DOI]

Sipra Das Bit

Proceedings of the IEEE International Conference on Systems, 2005

Synthesis of Testable Finite State Machine Through Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Cost Optimal Design of Nonlinear CA based PRPG for Test Applications.

[BibT_eX]

[DOI]

Hafizur Rahaman

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Design and characterization of cellular automata based associative memory for pattern recognition.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Part B, 2004

Generation of test patterns without prohibited pattern set.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

CA Based Document Compression Technology.

[BibT_eX]

[DOI]

Chandrama Shaw

N. C. Maiti

Proceedings of the Neural Information Processing, 11th International Conference, 2004

Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults.

[BibT_eX]

[DOI]

Anirban Kundu

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

An efficient design of non-linear CA based PRPG for VLSI circuit testing.

[BibT_eX]

[DOI]

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Cellular Automata Based Encompression Technology for Voice Data.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2004

Cellular Automata Evolution for Pattern Classification.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2004

Cellular Automata Evolution for Distributed Data Mining.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2004

Characterization of Reachable/Nonreachable Cellular Automata States.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2004

2003

Theory and Application of Cellular Automata For Pattern Classification.

[BibT_eX]

[DOI]

Fundam. Informaticae, 2003

Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines.

[BibT_eX]

[DOI]

Ujjwal Maulik

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Design Of A Universal BIST (UBIST) Structure.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Power Conscious BIST Design for Sequential Circuits Using ghost-FSM.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Efficient BIST design for sequential machines using FiF-FoF values in machine states.

[BibT_eX]

[DOI]

Sanghamitra Bandyopadhyay

Ujjwal Maulik

Subhadip Basu

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Design of hierarchical cellular automata for on-chip test pattern generator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Generalized Multiple Attractor Cellular Automata (GMACA) Model for Associative Memory.

[BibT_eX]

[DOI]

Int. J. Pattern Recognit. Artif. Intell., 2002

Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS).

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS).

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Characterization of Non-linear Cellular Automata Model for Pattern Recognition.

[BibT_eX]

[DOI]

Proceedings of the Advances in Soft Computing, 2002

Evolving Cellular Automata as Pattern Classifier.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2002

2001

Hierarchical Cellular Automata As An On-Chip Test Pattern Generator.

[BibT_eX]

[DOI]

Purnabha Majumder

Monalisa Mukherjee

Debesh K. Das

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits.

[BibT_eX]

[DOI]

Purnabha Majumder

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Evolving Cellular Automata Based Associative Memory for Pattern Recognition.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001

Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis.

[BibT_eX]

[DOI]

Debesh K. Das

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits.

[BibT_eX]

[DOI]

Aniket Karmakar

Subha Sankar Chowdhury

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Cellular automata as a built in self test structure.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.

[BibT_eX]

[DOI]

Kolin Paul

Gosta Pada Biswas

Vamsi Boppana

Cliff Yang

Sobhan Mukherjee

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images.

[BibT_eX]

[DOI]

Kolin Paul

Ranadeep Ghosal

Santashil Pal Chaudhuri

Dipanwita Roy Chowdhury

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Theory and Applications of Cellular Automata for VLSI Design and Testing.

[BibT_eX]

[DOI]

Dipanwita Roy Chowdhury

Kolin Paul