Marcel Runge

Orcid: 0000-0003-2540-1217

According to our database1, Marcel Runge authored at least 20 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter.
IEEE J. Solid State Circuits, 2023

A 4.4 GS/s 220 MHz ΣΔ ADC with a Linearized Back-Gate Controlled GmC Filter.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
A Calibration-Free 96.7 dB SNDR 4 MS/s CT I-SD Modulator With Single Feedback DAC.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

A 30-MHz BW 74.6-dB SNDR 92-dB SFDR CT ΔΣ Modulator with Active Body-Bias DAC Calibration in 22nm FDSOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX<sup>®</sup>.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Dynamic Body-Bias Linearization Technique Enabling Wide-Band GmC based Continous-Time Sigma-Delta Converters in 22 nm FD-SOI CMOS.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A 0.9V 45MS/s CT ΔΣ Modulator with 94dB SFDR and 25.6fJ/conv. enabled by a Digital Static and ISI Calibration in 22 FDSOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

A 18MS/s 76dB SNDR 93dB SFDR CT ΔΣ Modulator with Input Voltage Tracking 2nd-Order GmVC Filter and Shared FIR DAC in 22nm FDSOI CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A DAC Linearization Technique Enabling 15-Bit INL through Adaptive Body-Biasing in 22FDX.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 64 GBaud 6-Bit Current Steering DAC With a Binary Tree Current Summing Network.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Optimized Zero Placement within Noise Coupling Transfer Functions for Oversampled ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Body-Bias Techniques in CMOS 22FDX® for Mixed-Signal Circuits and Systems.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
A Temperature and Process Corner Insensitive Design Method for Digital Circuits in 40nm CMOS.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

AMDAC Common-Mode Shifting Technique enabling Power Consumption Reduction in Pipeline ADCs.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Correlation Based Time-Variant DAC Error Estimation in Continuous-Time ∑Δ ADCs With Pseudo Random Noise.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
Noise and non-linearity analysis of a charge-injection-cell-based 10-bit 50-MS/s SAR-ADC.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A digital compensation method canceling static and non-linear time-variant feedback DAC errors in ΣΔ analog-to-digital converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017


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