Marco Procaccini

Orcid: 0000-0002-9719-2672

According to our database1, Marco Procaccini authored at least 10 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Accelerating Large-Scale Graph Processing with FPGAs: Lesson Learned and Future Directions.
Proceedings of the 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2024

2023
Distributed large-scale graph processing on FPGAs.
J. Big Data, December, 2023

2021
The AXIOM Project: IoT on Heterogeneous Embedded Platforms.
IEEE Des. Test, 2021

DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model.
Proceedings of the Architecture of Computing Systems - 34th International Conference, 2021

2019
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS).
Int. J. Reconfigurable Comput., 2019

A Design Space Exploration Tool Set for Future 1K-core High-Performance Computers.
Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, 2019

Analyzing the Impact of Operating System Activity of Different Linux Distributions in a Distributed Environment.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019

Bridging a Data-Flow Execution Model to a Lightweight Programming Model.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

AXIOM: A Scalable, Efficient and Reconfigurable Embedded Platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Energy Efficiency Exploration on the ZYNQ Ultrascale+.
Proceedings of the 30th International Conference on Microelectronics, 2018


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