Wayne Luk

According to our database1, Wayne Luk authored at least 520 papers between 1990 and 2019.

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Awards

IEEE Fellow

IEEE Fellow 2009, "For contributions to reconfigurable computing".

Timeline

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Bibliography

2019
Performance Tuning and Analysis for Stencil-Based Applications on POWER8 Processor.
TACO, 2019

A Real-Time Tree Crown Detection Approach for Large-Scale Remote Sensing Images on FPGAs.
Remote Sensing, 2019

Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going.
ACM Comput. Surv., 2019

On-chip FPGA Debug Instrumentation for Machine Learning Applications.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Memory Mapping for Multi-die FPGAs.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Optimizing CNN-Based Hyperspectral Image Classification on FPGAs.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies.
Signal Processing Systems, 2018

Stream Processing Dual-Track CGRA for Object Inference.
IEEE Trans. VLSI Syst., 2018

Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA.
TRETS, 2018

FP-BNN: Binarized neural network on FPGA.
Neurocomputing, 2018

Correlation Coefficient Based Cluster Data Preprocessing and LSTM Prediction Model for Time Series Data in Large Aircraft Test Flights.
Proceedings of the Smart Computing and Communication - Third International Conference, 2018

Reconfigurable Hardware Generation for Tensor Flow Models of CNN Algorithms on a Heterogeneous Acceleration Platform.
Proceedings of the Smart Computing and Communication - Third International Conference, 2018

Custom machine learning architectures: towards realtime anomaly detection for flight testing.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

RAW 2018 Invited Talks.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

CJS: Custom Jacobi Solver.
Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

Performance Estimation for Exascale Reconfigurable Dataflow Platforms.
Proceedings of the International Conference on Field-Programmable Technology, 2018

FLiMS: Fast Lightweight Merge Sorter.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Memory-Efficient Architecture for Accelerating Generative Networks on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Lossy Multiport Memory.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Scheduling Algorithms for High Performance Network Switching on FPGAs: A Survey.
Proceedings of the International Conference on Field-Programmable Technology, 2018

A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Accelerating Database Systems Using FPGAs: A Survey.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

CRRS: Custom Regression and Regularisation Solver for Large-Scale Linear Systems.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Performance Prediction for Large-Scale Heterogeneous Platforms.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Hardware Compilation of Deep Neural Networks: An Overview.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis.
IEEE Trans. VLSI Syst., 2017

The First 25 Years of the FPL Conference: Significant Papers.
TRETS, 2017

Efficient Assembly for High-Order Unstructured FEM Meshes (FPL 2015).
TRETS, 2017

A Domain Specific Approach to High Performance Heterogeneous Computing.
IEEE Trans. Parallel Distrib. Syst., 2017

Leveraging FPGAs for Accelerating Short Read Alignment.
IEEE/ACM Trans. Comput. Biology Bioinform., 2017

Transparent In-Circuit Assertions for FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

A Fully-Pipelined Hardware Design for Gaussian Mixture Models.
IEEE Trans. Computers, 2017

Solving Mesoscale Atmospheric Dynamics Using a Reconfigurable Dataflow Architecture.
IEEE Micro, 2017

ADvaNCE - Efficient and Scalable Approximate Density-Based Clustering Based on Hashing.
Informatica, Lith. Acad. Sci., 2017

Exploiting the chaotic behaviour of atmospheric models with reconfigurable architectures.
Computer Physics Communications, 2017

Chapter Four - Data Flow Computing in Geoscience Applications.
Advances in Computers, 2017

Chapter Two - Advances in Dataflow Systems.
Advances in Computers, 2017

FEM-based soft robotic control framework for intracavitary navigation.
Proceedings of the 2017 IEEE International Conference on Real-time Computing and Robotics, 2017

Hardware Acceleration for Machine Learning.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Convolutional Neural Networks on Dataflow Engines.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

An FPGA-based tree crown detection approach for remote sensing images.
Proceedings of the International Conference on Field Programmable Technology, 2017

Validating optimisations for chaotic simulations.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Customised pearlmutter propagation: A hardware architecture for trust region policy optimisation.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Exploring the potential of reconfigurable platforms for order book update.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

F-C3D: FPGA-based 3-dimensional convolutional neural network.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Accelerating Financial Market Server through Hybrid List Design (Abstract Only).
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

A Nanosecond-Level Hybrid Table Design for Financial Market Data Generators.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

DeepPump: Multi-pumping deep Neural Networks.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

Custom Framework for Run-Time Trading Strategies.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

In-Circuit Assertions and Exceptions for Reconfigurable Hardware Design.
Proceedings of the Provably Correct Systems, 2017

2016
Self-adaptive Hardware Acceleration on a Heterogeneous Cluster.
Proceedings of the Self-aware Computing Systems - An Engineering Approach, 2016

Self-aware Hardware Acceleration of Financial Applications on a Heterogeneous Cluster.
Proceedings of the Self-aware Computing Systems - An Engineering Approach, 2016

An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating.
IEEE Trans. VLSI Syst., 2016

Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach.
Softw., Pract. Exper., 2016

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Dataflow design for optimal incremental SVM training.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

CASK: Open-Source Custom Architectures for Sparse Kernels.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

F-CNN: An FPGA-based framework for training Convolutional Neural Networks.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

Relation-oriented resource allocation for multi-accelerator systems.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

A Domain Specific Language for accelerated Multilevel Monte Carlo simulations.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

Hashing-Based Approximate DBSCAN.
Proceedings of the Advances in Databases and Information Systems, 2016

2015
Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems.
IEEE Trans. VLSI Syst., 2015

Automating Elimination of Idle Functions by Runtime Reconfiguration.
TRETS, 2015

Solving the Global Atmospheric Equations through Heterogeneous Reconfigurable Platforms.
TRETS, 2015

Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems.
TRETS, 2015

A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution.
SIGARCH Computer Architecture News, 2015

Parallel Genetic Algorithms on Multiple FPGAs.
SIGARCH Computer Architecture News, 2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

A general-purpose framework for FPGA-accelerated genetic algorithms.
IJBIC, 2015

Network-Level FPGA Acceleration of Low Latency Market Data Feed Arbitration.
IEICE Transactions, 2015

Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

RAW Introduction and Committees.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

GPU-based proximity query processing on unstructured triangular mesh model.
Proceedings of the IEEE International Conference on Robotics and Automation, 2015

Lower precision for higher accuracy: Precision and resolution exploration for shallow water equations.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

FPGA acceleration of reference-based compression for genomic data.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Recursive pipelined genetic propagation for bilevel optimisation.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Significant papers from the first 25 years of the FPL conference.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Preface.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Efficient assembly for high order unstructured FEM meshes.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Delay-Bounded Routing for Shadow Registers.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Architectures and Precision Analysis for Modelling Atmospheric Variables with Chaotic Behaviour.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Pipelined Genetic Propagation.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Accelerating SpMV on FPGAs by Compressing Nonzero Values.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

In-circuit temporal monitors for runtime verification of reconfigurable designs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

HW/SW Partitioning Algorithm Targeting MPSOC with Dynamic Partial Reconfigurable Fabric.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

Reconfigurable acceleration of fitness evaluation in trading strategies.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Pipelined HAC Estimation Engines for Multivariate Time Series.
Signal Processing Systems, 2014

Mapping Loop Structures Onto Parametrized Hardware Pipelines.
IEEE Trans. VLSI Syst., 2014

A Self-Aware Tuning and Self-Aware Evaluation Method for Finite-Difference Applications in Reconfigurable Systems.
TRETS, 2014

Hardware Acceleration for an Accurate Stereo Vision System Using Mini-Census Adaptive Support Region.
ACM Trans. Embedded Comput. Syst., 2014

Using Statistical Assertions to Guide Self-Adaptive Systems.
Int. J. Reconfig. Comp., 2014

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

Elastic Management of Reconfigurable Accelerators.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

A Hybrid Genetic-Programming Swarm-Optimisation Approach for Examining the Nature and Stability of High Frequency Trading Strategies.
Proceedings of the 13th International Conference on Machine Learning and Applications, 2014

HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Collaborative processing of Least-Square Monte Carlo for American options.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Accelerating transfer entropy computation.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Is high level synthesis ready for business? A computational finance case study.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

A dataflow system for anomaly detection and analysis.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Patra: Parallel tree-reweighted message passing architecture.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Transparent insertion of latency-oblivious logic onto FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Automated framework for FPGA-based parallel genetic algorithms.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A highly-efficient and green data flow engine for solving euler atmospheric equations.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

An efficient sparse conjugate gradient solver using a Beneš permutation network.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Dataflow acceleration of Krylov subspace sparse banded problems.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Accelerating parameter estimation for multivariate self-exciting point processes.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Automating Optimization of Reconfigurable Designs.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Automated Framework for General-Purpose Genetic Algorithms in FPGAs.
Proceedings of the Applications of Evolutionary Computation - 17th European Conference, 2014

An approach of processor core customization for stencil computation.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Pipelined reconfigurable accelerator for ordinal pattern encoding.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Low latency FPGA acceleration of market data feed arbitration.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Effective Reconfigurable Design: The FASTER Approach.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

HARNESS Project: Managing Heterogeneous Computing Resources for a Cloud Platform.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model.
IEEE Trans. VLSI Syst., 2013

Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs.
IEEE Trans. VLSI Syst., 2013

The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures.
IEEE Trans. VLSI Syst., 2013

Dimensionality Reduction in Controlling Articulated Snake Robot for Endoscopy Under Dynamic Active Constraints.
IEEE Trans. Robotics, 2013

Customisable architectures for the set covering problem.
SIGARCH Computer Architecture News, 2013

Customisable pipelined engine for intensity evaluation in multivariate hawkes point processes.
SIGARCH Computer Architecture News, 2013

Accelerating sequential Monte Carlo method for real-time air traffic management.
SIGARCH Computer Architecture News, 2013

Controlling a complete hardware synthesis toolchain with LARA aspects.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Parallel partitioning for distributed systems using sequential assignment.
J. Parallel Distrib. Comput., 2013

Parallel neighbourhood search on many-core platforms.
IJCSE, 2013

Scalable Session Programming for Heterogeneous High-Performance Systems.
Proceedings of the Software Engineering and Formal Methods, 2013

A framework for effective exploitation of partial reconfiguration in dataflow computing.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

RALP: Reconvergence-aware layer partitioning for 3D FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

A Heterogeneous Computing Framework for Computational Finance.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Application-specific customisation of market data feed arbitration.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Acceleration of real-time Proximity Query for dynamic active constraints.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Reconfigurable filtered acceleration of short read alignment.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Runtime assertions and exceptions for streaming systems.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A scalable design approach for stencil computation on reconfigurable clusters.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Accelerating maximum likelihood estimation for Hawkes point processes.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Accelerating solvers for global atmospheric equations through mixed-precision data flow engine.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Automating resource optimisation in reconfigurable design (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

An FPGA-Based Data Flow Engine for Gaussian Copula Model.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Automating Elimination of Idle Functions by Run-Time Reconfiguration.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Global Atmospheric Simulation on a Reconfigurable Platform.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Reconfigurable Acceleration of Short Read Mapping.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Parallelisation of Sequential Monte Carlo for real-time control in air traffic management.
Proceedings of the 52nd IEEE Conference on Decision and Control, 2013

Accelerating HAC estimation for multivariate time series.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Aspect driven compilation for dataflow designs.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

Parametric Optimization of Reconfigurable Designs Using Machine Learning.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

Hardware Acceleration of Genetic Sequence Alignment.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012
Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms.
Signal Processing Systems, 2012

Optimizing Floating Point Units in Hybrid FPGAs.
IEEE Trans. VLSI Syst., 2012

Design Exploration of Quadrature Methods in Option Pricing.
IEEE Trans. VLSI Syst., 2012

FISH: Fast Instruction SyntHesis for Custom Processors.
IEEE Trans. VLSI Syst., 2012

Optimizing Hardware Design by Composing Utility-Directed Transformations.
IEEE Trans. Computers, 2012

Modelling reconfigurable systems in event driven simulation.
SIGARCH Computer Architecture News, 2012

Roberts: reconfigurable platform for benchmarking real-time systems.
SIGARCH Computer Architecture News, 2012

Improving communication latency with the write-only architecture.
J. Parallel Distrib. Comput., 2012

Robust Software Partitioning with Multiple Instantiation.
INFORMS Journal on Computing, 2012

Reconfigurable FPGA-based switching path frequency-domain echo canceller with applications to voice control device.
Digital Signal Processing, 2012

Smart technologies for effective reconfiguration: The FASTER approach.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Evaluating reconfigurable dataflow computing using the Himeno benchmark.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Self-Adaptive Heterogeneous Cluster with Wireless Network.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

A Large-Scale Spiking Neural Network Accelerator for FPGA Systems.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2012, 2012

A partially reconfigurable architecture supporting hardware threads.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Verification of streaming hardware and software codesigns.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

FPGA based memory efficient high resolution stereo vision system for video tolling.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Parametric reconfigurable designs with Machine Learning Optimizer.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

A fully-pipelined expectation-maximization engine for Gaussian Mixture Models.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Verification of streaming designs by combining symbolic simulation and equivalence checking.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Exploiting run-time reconfiguration in stencil computation.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Detecting power attacks on reconfigurable hardware.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Optimising explicit finite difference option pricing for dynamic constant reconfiguration.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Adaptive Sequential Monte Carlo approach for real-time applications.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A mixed precision Monte Carlo methodology for reconfigurable accelerator systems.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

A Mixed Precision Methodology for Mathematical Optimisation.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Specifying Compiler Strategies for FPGA-based Systems.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Controlling Hardware Synthesis with Aspects.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Resource-Efficient Designs Using an Aspect-Oriented Approach.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Reconfigurable Design Automation by High-Level Exploration.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

Optimising Performance of Quadrature Methods with Reduced Precision.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

Heterogeneous Systems for Energy Efficient Scientific Computing.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

Efficient Communication for FPGA Clusters.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

Experiments with the LARA aspect-oriented approach.
Proceedings of the Companion Volume of the 11th International Conference on Aspect-oriented Software Development, 2012

LARA: an aspect-oriented programming language for embedded systems.
Proceedings of the 11th International Conference on Aspect-oriented Software Development, 2012

2011
Design Optimizations for Tiled Partially Reconfigurable Systems.
IEEE Trans. VLSI Syst., 2011

An Analytical Model Relating FPGA Architecture to Logic Density and Depth.
IEEE Trans. VLSI Syst., 2011

Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network.
IEEE Trans. Industrial Electronics, 2011

Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation.
Trans. HiPEAC, 2011

A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors.
Trans. HiPEAC, 2011

Power profiling and optimization for heterogeneous multi-core systems.
SIGARCH Computer Architecture News, 2011

Parametrized hardware architectures for the Lucas primality test.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Power adaptive computing system design in energy harvesting environment.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Customisable Multi-Processor Acceleration of Inductive Logic Programming.
Proceedings of the Latest Advances in Inductive Logic Programming, 2011

Hydrate: Hybrid Reconfigurable Architecture Expressions.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Automating formal verification of customized soft-processors.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Constant power reconfigurable computing.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Objective-driven workload allocation in heterogeneous computing systems.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

A framework for FPGA acceleration of large graph problems: Graphlet counting case study.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Unifying Finite Difference Option-Pricing for Hardware Acceleration.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

On Comparing Financial Option Price Solvers on FPGA.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Mixed Precision Processing in Reconfigurable Systems.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

CusComNet: A customisable network for reconfigurable heterogeneous clusters.
Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011

FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain.
ACM Trans. Design Autom. Electr. Syst., 2010

FPGA Designs with Optimized Logarithmic Arithmetic.
IEEE Trans. Computers, 2010

Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study.
IEEE Trans. Computers, 2010

Programming framework for clusters with heterogeneous accelerators.
SIGARCH Computer Architecture News, 2010

Efficient reconfigurable design for pricing asian options.
SIGARCH Computer Architecture News, 2010

HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.
IEEE Micro, 2010

Wave-pipelined intra-chip signaling for on-FPGA communications.
Integration, 2010

Multiloop Parallelisation Using Unrolling and Fission.
Int. J. Reconfig. Comp., 2010

Power Characterisation for Fine-Grain Reconfigurable Fabrics.
Int. J. Reconfig. Comp., 2010

Automated placement of reconfigurable regions for relocatable modules.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Towards an embedded biologically-inspired machine vision processor.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Convex models for accelerating applications on FPGA-based clusters.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A Karatsuba-Based Montgomery Multiplier.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Axel: a heterogeneous cluster with FPGAs and GPUs.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

A Scripting Engine for Combining Design Transformations.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Energy-Aware Optimisation for Run-Time Reconfiguration.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Customizable Composition and Parameterization of Hardware Design Transformations.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Exploration of hardware sharing for image encoders.
Proceedings of the Design, Automation and Test in Europe, 2010

Combining optimizations in automated low power design.
Proceedings of the Design, Automation and Test in Europe, 2010

Exploring algorithmic trading in reconfigurable hardware.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

Design space exploration of parametric pipelined designs.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

Parametric Encryption Hardware Design.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Hierarchical Segmentation for Hardware Function Evaluation.
IEEE Trans. VLSI Syst., 2009

Floating-Point FPGA: Architecture and Modeling.
IEEE Trans. VLSI Syst., 2009

Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models.
TRETS, 2009

High-throughput one-dimensional median and weighted median filters on FPGA.
IET Computers & Digital Techniques, 2009

Accelerating Seismic Computations Using Customized Number Representations on FPGAs.
EURASIP J. Emb. Sys., 2009

Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation.
Proceedings of the SOFSEM 2009: Theory and Practice of Computer Science, 2009

A high-level compilation toolchain for heterogeneous systems.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Tuning instruction customisation for reconfigurable system-on-chip.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

FPGA Accelerated Low-Latency Market Data Feed Processing.
Proceedings of the 17th IEEE Symposium on High Performance Interconnects, 2009

Optimising designs by combining model-based and pattern-based transformations.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Exploring reconfigurable architectures for explicit finite difference option pricing models.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Modeling post-techmapping and post-clustering FPGA circuit depth.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Accelerating Quadrature Methods for Option Valuation.
Proceedings of the FCCM 2009, 2009

FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks.
Proceedings of the FCCM 2009, 2009

Benchmarking Reconfigurable Architectures in the Mobile Domain.
Proceedings of the FCCM 2009, 2009

Harnessing Human Computation Cycles for the FPGA Placement Problem.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

Partition-based exploration for reconfigurable JPEG designs.
Proceedings of the Design, Automation and Test in Europe, 2009

Design optimizations to improve placeability of partial reconfiguration modules.
Proceedings of the Design, Automation and Test in Europe, 2009

A DP-network for optimal dynamic routing in network-on-chip.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Accelerating a Virtual Ecology Model with FPGAs.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

Parametric Design for Reconfigurable Software-Defined Radio.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Guest Editorial: 20 Years of ASAP.
Signal Processing Systems, 2008

Reconfigurable Architecture for Network Flow Analysis.
IEEE Trans. VLSI Syst., 2008

A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications.
TRETS, 2008

Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware.
TRETS, 2008

Introduction.
TRETS, 2008

CHIPS: Custom Hardware Instruction Processor Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations.
IEEE Trans. Computers, 2008

Custom parallel caching schemes for hardware-accelerated image compression.
J. Real-Time Image Processing, 2008

The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units.
Int. J. Reconfig. Comp., 2008

Interconnection lengths and delays estimation for communication links in FPGAs.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Global interconnections in FPGAs: modeling and performance analysis.
Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Reconfigurable design with clock gating.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Systematic design space exploration for customisable multi-processor architectures.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Smart Enumeration: A Systematic Approach to Exhaustive Search.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Implementation of Wave-Pipelined Interconnects in FPGAs.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Optimizing coarse-grained units in floating point hybrid FPGA.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Estimation of sample mean and variance for Monte-Carlo simulations.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Wave-pipelined signaling for on-FPGA communication.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Unrolling-based loop mapping and scheduling.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Optimizing residue arithmetic on FPGAs.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Sampling from the exponential distribution using independent Bernoulli variates.
Proceedings of the FPL 2008, 2008

An analytical model describing the relationships between logic architecture and FPGA density.
Proceedings of the FPL 2008, 2008

Mapping and scheduling with task clustering for heterogeneous computing systems.
Proceedings of the FPL 2008, 2008

A hardware compilation flow for instance-specific VLIW cores.
Proceedings of the FPL 2008, 2008

Rapid estimation of power consumption for hybrid FPGAs.
Proceedings of the FPL 2008, 2008

Towards benchmarking energy efficiency of reconfigurable architectures.
Proceedings of the FPL 2008, 2008

FPGA-optimised high-quality uniform random number generators.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

High-throughput interconnect wave-pipelining for global communication in FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Power-Aware and Branch-Aware Word-Length Optimization.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Using Reconfigurable Logic to Optimise GPU Memory Accesses.
Proceedings of the Design, Automation and Test in Europe, 2008

A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming.
Proceedings of the Visions of Computer Science, 2008

Reconfigurable acceleration of microphone array algorithms for speech enhancement.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Resource efficient generators for the floating-point uniform and exponential distributions.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Fast custom instruction identification by convex subgraph enumeration.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models.
Proceedings of the Reconfigurable Computing: Architectures, 2008

An FPGA run-time parameterisable Log-Normal Random Number Generator.
Proceedings of the Reconfigurable Computing: Architectures, 2008

An Overview of Low-Power Techniques for Field-Programmable Gate Arrays.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices.
VLSI Signal Processing, 2007

Designing a Posture Analysis System with Hardware Implementation.
VLSI Signal Processing, 2007

Run-Time Integration of Reconfigurable Video Processing Systems.
IEEE Trans. VLSI Syst., 2007

Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method.
IEEE Trans. VLSI Syst., 2007

High-Performance Embedded Architecture and Compilation Roadmap.
Trans. HiPEAC, 2007

Real-time hardware acceleration of the trace transform.
J. Real-Time Image Processing, 2007

Gaussian random number generators.
ACM Comput. Surv., 2007

Domain Specific Transformations for Hardware Ray Tracing.
Proceedings of the 30th Communicating Process Architectures Conference, 2007

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Improving Bounds for FPGA Logic Minimization.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

FPGA-based Streaming Computation for Lattice Boltzmann Method.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Instrumented Multi-Stage Word-Length Optimization.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Unifying FPGA Hardware Development.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems.
Proceedings of the FPL 2007, 2007

Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications.
Proceedings of the FPL 2007, 2007

A synthesizable datapath-oriented embedded FPGA fabric.
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Optimizing Logarithmic Arithmetic on FPGAs.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

A Hybrid Memory Sub-system for Video Coding Applications.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

Optimizing instruction-set extensible processors under data bandwidth constraints.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Reconfigurable Hardware Acceleration of Canonical Graph Labelling.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Accuracy-Guaranteed Bit-Width Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis.
IEEE Trans. Computers, 2006

Dynamic clock-frequencies for FPGAs.
Microprocessors and Microsystems, 2006

Provably-correct hardware compilation tools based on pass separation techniques.
Formal Asp. Comput., 2006

On-Chip Communication in Run-Time Assembled Reconfigurable Systems.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

A Reconfigurable Simulation Framework for Financial Computation.
Proceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, 2006

Hardware architectures for Monte-Carlo based financial simulations.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Comparing floating-point and logarithmic number representations for reconfigurable acceleration.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

An FPGA implementation of the simplex algorithm.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

The cost of data dependence in motion vector estimation for reconfigurable platforms.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Non-Uniform Random Number Generation Through Piecewise Linear Approximations.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

On-FPGA Communication Architectures and Design Factors.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Efficient Realtime FPGA Implementation of the Trace Transform.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Efficient Hardware Generation of Random Variates with Arbitrary Distributions.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Generating Parametrised Hardware Libraries from Higher-Order Descriptions.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Automating processor customisation: optimised memory access and resource sharing.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Incremental elaboration for run-time reconfigurable hardware designs.
Proceedings of the 2006 International Conference on Compilers, 2006

UNITE: Uniform Hardware-Based Network Intrusion deTection Engine.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

A Flexible Multi-port Caching Scheme for Reconfigurable Platforms.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
A hardware Gaussian noise generator using the Wallace method.
IEEE Trans. VLSI Syst., 2005

Optimum and heuristic synthesis of multiple word-length architectures.
IEEE Trans. VLSI Syst., 2005

Customizable elliptic curve cryptosystems.
IEEE Trans. VLSI Syst., 2005

Optimizing Hardware Function Evaluation.
IEEE Trans. Computers, 2005

High quality uniform random number generation for massively parallel simulations in FPGA.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

Quartz: a framework for correct and efficient reconfigurable design.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

Reconfigurable Acceleration for Monte Carlo Based Financial Simulation.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Custom Hardware Architectures for Posture Analysis.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

An Overview of High-Level Synthesis of Multiprocessors for Logic Programming.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Have GPUs Made FPGAs Redundant in the Field of Video Processing?
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Dynamic Voltage Scaling for Commercial FPGAs.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Ziggurat-based Hardware Gaussian Random Number Generator.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Bitwise Optimised CAM for Network Intrusion Detection Systems.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Compilation and Management of Phase-Optimized Reconfigurable Systems.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Reconfigurable Designs for Radiosity.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

Cell Based Motion Estimators for Reconfigurable Platforms.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

A Combined Hardware-Software Architecture for Network Flow.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

Hardware Acceleration of Hidden Markov Model Decoding for Person Detection.
Proceedings of the 2005 Design, 2005

Reconfigurable Elliptic Curve Cryptosystems on a Chip.
Proceedings of the 2005 Design, 2005

MiniBit: bit-width optimization via affine arithmetic.
Proceedings of the 42nd Design Automation Conference, 2005

Resolving Quartz Overloading.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

Automating custom-precision function evaluation for embedded processors.
Proceedings of the 2005 International Conference on Compilers, 2005

Customising Application-Speci.c Multiprocessor Systems: a Case Study.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Parameterized High Throughput Function Evaluation for FPGAs.
VLSI Signal Processing, 2004

Exploiting Program Branch Probabilities in Hardware Compilation.
IEEE Trans. Computers, 2004

A Gaussian Noise Generator for Hardware-Based Simulations.
IEEE Trans. Computers, 2004

Customising Hardware Designs for Elliptic Curve Cryptography.
Proceedings of the Computer Systems: Architectures, 2004

Customising Processors: Design-Time and Run-Time Opportunities.
Proceedings of the Computer Systems: Architectures, 2004

Autonomous Memory Block for reconfigurable computing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Memory optimisations for high-resolution imaging.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Pipelining designs with loop-carried dependencies.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Scalable structured data access by combining autonomous memory blocks.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

Adaptive range reduction for hardware function evaluation.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

A scalable hardware architecture for prime number validation.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays.
Proceedings of the Field Programmable Logic and Application, 2004

Methods and Tools for High-Resolution Imaging.
Proceedings of the Field Programmable Logic and Application, 2004

Implementing Graphics Shaders Using FPGAs.
Proceedings of the Field Programmable Logic and Application, 2004

A Structured Methodology for System-on-an-FPGA Design.
Proceedings of the Field Programmable Logic and Application, 2004

SoftSONIC: A Customisable Modular Platform for Video Applications.
Proceedings of the Field Programmable Logic and Application, 2004

Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs.
Proceedings of the Field Programmable Logic and Application, 2004

A Structured System Methodology for FPGA Based System-on-A-Chip Design.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

A Flexible Hardware Encoder for Low-Density Parity-Check Codes.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Customisable Hardware Compilation.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

Evaluation of SystemC Modelling of Reconfigurable Embedded Systems.
Proceedings of the 2004 Design, 2004

Customisable EPIC Processor: Architecture and Tools.
Proceedings of the 2004 Design, 2004

Synthesis and optimization of DSP algorithms.
Kluwer, ISBN: 978-1-4020-7930-6, 2004

2003
Synthesis of saturation arithmetic architectures.
ACM Trans. Design Autom. Electr. Syst., 2003

Wordlength optimization for linear digital signal processing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Multitasking in hardware-software codesign for reconfigurable computer.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Combining Imperative and Declarative Hardware Descriptions.
Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003

Towards Verifying Parametrised Hardware Libraries with Relative Placement Information.
Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003

Design space exploration with A Stream Compiler.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Hierarchical segmentation schemes for function evaluation.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

High-level language extensions for run-time reconfigurable systems.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

FPGA-based computation of free-form deformations in medical image registration.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Customising parallelism and caching for machine learning.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Source-directed transformations for hardware compilation.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Branch Optimisation Techniques for Hardware Compilation.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

A Reconfigurable Platform for Real-Time Embedded Video Image Processing.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Irregular Reconfigurable CAM Structures for Firewall Applications.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Non-uniform Segmentation for Hardware Function Evaluation.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

FPGA-Based Computation of Free-Form Deformations.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Hardware Design with a Scripting Language.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Real-time Extensions to a C-like Hardware Description Language.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

Compiling Policy Descriptions into Reconfigurable Firewall Processors.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

A Hardware Gaussian Noise Generator for Channel Code Evaluation.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

PyHDL: Hardware Scripting with Python.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2002
Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign.
Design Autom. for Emb. Sys., 2002

PD-XML: extensible markup language for processor description.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Development framework for firewall processors.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Incremental programming for reconfigurable engines.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

FPGA-based computation of free-form deformations.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Strassen's matrix multiplication for customisable processors.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Floating-point bitwidth analysis via automatic differentiation.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Scalable acceleration of inductive logic programs.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Compiling run-time parametrisable designs.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Optimising and adapting high-level hardware designs.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Run-Time Adaptive Flexible Instruction Processors.
Proceedings of the Field-Programmable Logic and Applications, 2002

Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer.
Proceedings of the Field-Programmable Logic and Applications, 2002

Automating Customisation of Floating-Point Designs.
Proceedings of the Field-Programmable Logic and Applications, 2002

Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries.
Proceedings of the Formal Methods in Computer-Aided Design, 4th International Conference, 2002

Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Accelerating Radiosity Calculations Using Reconfigurable Platforms.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Reconfigurable Shape-Adaptive Template Matching Architectures.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Customising Floating-Point Designs.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Optimum Wordlength Allocation.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001
Quantitative Analysis of FPGA-based Database Searching.
VLSI Signal Processing, 2001

Pipeline vectorization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

An integrated system for developing regular array designs.
Journal of Systems Architecture, 2001

Parameterised floating-point arithmetic on FPGAs.
Proceedings of the IEEE International Conference on Acoustics, 2001

Task-Parallel Programming of Reconfigurable Systems.
Proceedings of the Field-Programmable Logic and Applications, 2001

A Digit-Serial Structure for Reconfigurable Multipliers.
Proceedings of the Field-Programmable Logic and Applications, 2001

Parameterized Function Evaluation for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2001

Reconfigurable Designs for Ray Tracing.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

The Effect of FPGA Granularity on Video Codec Implementations.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

The Multiple Wordlength Paradigm.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Pipelined Function Evaluation on FPGAs.
Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Heuristic datapath allocation for multiple wordlength systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques.
Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000
Guest Editors' Introduction.
VLSI Signal Processing, 2000

Video Image Processing with the Sonic Architecture.
IEEE Computer, 2000

Roundoff-noise shaping in filter design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems.
Proceedings of the Field-Programmable Logic and Applications, 2000

Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT.
Proceedings of the Field-Programmable Logic and Applications, 2000

Combining Serialisation and Reconfiguration for FPGA Designs.
Proceedings of the Field-Programmable Logic and Applications, 2000

Multiple-Wordlength Resource Binding.
Proceedings of the Field-Programmable Logic and Applications, 2000

Evaluating Hardware Compilation Techniques.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Customizing Graphics Applications: Techniques and Programming Interface.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Combining Serialization and Reconfiguration for Convolver Designs.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Multiple Precision for Resource Minimization.
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

Flexible instruction processors.
Proceedings of the 2000 International Conference on Compilers, 2000

1999
Memory Access Optimization and RAM Inference for Pipeline Vectorization.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Quantitative Analysis of Run-Time Reconfigurable Database Search.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Serial Hardware Libraries for Reconfigurable Designs.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

SONIC - A Plug-In Architecture for Video Processing.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Towards Adaptable Hierarchical Placement for FPGAs.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Pipeline Vectorization for Reconfigurable Systems.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

Reconfigurable Computing for Augmented Reality.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

SONIC - A Plug-In Architecture for Video Processing.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

Optimizing FPGA-Based Vector Product Designs.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998
Run-Time Management of Dynamically Recongigurable Designs.
Proceedings of the Field-Programmable Logic and Applications, 1998

Pebble: A Language for Parametrised and Reconfigurable Hardware Design.
Proceedings of the Field-Programmable Logic and Applications, 1998

A Reconfigurable Engine for Real-Time Video Processing.
Proceedings of the Field-Programmable Logic and Applications, 1998

Automating Production of Run-Time Reconfigurable Designs.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
Verified Compilation of Communicating Processes into Clocked Circuits.
Formal Asp. Comput., 1997

Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Pipeline morphing and virtual pipelines.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

A reconfigurable data-localised array for morphological algorithms.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Compilation tools for run-time reconfigurable designs.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1996
Guest editors' introduction.
VLSI Signal Processing, 1996

Binomial filters.
VLSI Signal Processing, 1996

Retargeting a Hardware Compiler Using Protokol Converters.
Formal Asp. Comput., 1996

A Framework for Developing Parameterised FPGA Libraries.
Proceedings of the Field-Programmable Logic, 1996

Modelling and optimising run-time reconfigurable systems.
Proceedings of the 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), 1996

1995
Using Reconfigurable Hardware to Speed up Product Development and Performance.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

Compiling Ruby into FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

1994
Developing Parallel Architectures for Range and Image Sensors.
Proceedings of the 1994 International Conference on Robotics and Automation, 1994

Constraint-based Hierarchical Placement of Parallel Programs.
Proceedings of the Field-Programmable Logic, 1994

Towards a declarative framework for hardware-software codesign.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

Retargeting a hardware compiler proof using protocol converters.
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994

1993
Introduction.
VLSI Signal Processing, 1993

1990
A Systolic LRU Processor and Its Top-Down Development.
Sci. Comput. Program., 1990


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