Marcus Eggenberger

According to our database1, Marcus Eggenberger authored at least 8 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
Parallel Simulation of Networks on Chip.
PhD thesis, 2020

2017
Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip.
IEEE Trans. Computers, 2017

Low power memory allocation and mapping for area-constrained systems-on-chips.
EURASIP J. Embed. Syst., 2017

2016
Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

2015
Optimal memory selection for low power embedded systems.
Proceedings of the 12th International Workshop on Intelligent Solutions in Embedded Systems, 2015

2014
On Covering Structural Defects in NoCs by Functional Tests.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Scalable parallel simulation of networks on chip.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Fine grained adaptive simulation with application to NoCs.
Proceedings of the 2013 Forum on specification and Design Languages, 2013


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