Hans-Joachim Wunderlich

According to our database1, Hans-Joachim Wunderlich authored at least 245 papers between 1985 and 2021.

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Awards

IEEE Fellow

IEEE Fellow 2009, "For contributions to very-large-scale-integration circuit testing and fault tolerance".

Timeline

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Bibliography

2021
A Hybrid Protection Scheme for Reconfigurable Scan Networks.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020
Switch Level Time Simulation of CMOS Circuits with Adaptive Voltage and Frequency Scaling.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks.
Proceedings of the IEEE International Test Conference, 2020

Logic Fault Diagnosis of Hidden Delay Defects.
Proceedings of the IEEE International Test Conference, 2020

Variation-Aware Defect Characterization at Cell Level.
Proceedings of the IEEE European Test Symposium, 2020

GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency Scaling.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Synthesis of Fault-Tolerant Reconfigurable Scan Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Using Programmable Delay Monitors for Wear-Out and Early Life Failure Prediction.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
SWIFT: Switch-Level Fault Simulation on GPUs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Built-In Test for Hidden Delay Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Multi-level timing and fault simulation on GPUs.
Integr., 2019

Security Compliance Analysis of Reconfigurable Scan Networks.
Proceedings of the IEEE International Test Conference, 2019

Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses.
Proceedings of the IEEE International Test Conference, 2019

On Secure Data Flow in Reconfigurable Scan Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Guest Editors' Introduction.
IEEE Embed. Syst. Lett., 2018

Guest Editor's Introduction.
IEEE Des. Test, 2018

Self-Test and Diagnosis for Self-Aware Systems.
IEEE Des. Test, 2018

Detecting and Resolving Security Violations in Reconfigurable Scan Networks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Device aging: A reliability and security concern.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Online prevention of security violations in reconfigurable scan networks.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

Multi-level timing simulation on GPUs.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
GPU-Accelerated Simulation of Small Delay Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures.
IEEE Trans. Computers, 2017

Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip.
IEEE Trans. Computers, 2017

Aging monitor reuse for small delay fault testing.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Special session on early life failures.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Analysis and mitigation or IR-Drop induced scan shift-errors.
Proceedings of the IEEE International Test Conference, 2017

Trustworthy reconfigurable access to on-chip infrastructure.
Proceedings of the International Test Conference in Asia, 2017

Energy-efficient and error-resilient iterative solvers for approximate computing.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Probabilistic sensitization analysis for variation-aware path delay fault test evaluation.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Specification and verification of security in reconfigurable scan networks.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Structure-Oriented Test of Reconfigurable Scan Networks.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Fault tolerance of approximate compute algorithms.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Dependable on-chip infrastructure for dependable MPSOCs.
Proceedings of the 17th Latin-American Test Symposium, 2016

Pushing the limits: How fault tolerance extends the scope of approximate computing.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

ETS 2015 best paper.
Proceedings of the 21th IEEE European Test Symposium, 2016

Formal verification of secure reconfigurable scan network infrastructure.
Proceedings of the 21th IEEE European Test Symposium, 2016

Efficient Algorithm-Based Fault Tolerance for Sparse Matrix Operations.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2016

Applying efficient fault tolerance to enable the preconditioned conjugate gradient solver on approximate computing hardware.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Autonomous Testing for 3D-ICs with IEEE Std. 1687.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

High-Throughput Transistor-Level Fault Simulation on GPUs.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Test Strategies for Reconfigurable Scan Networks.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

A Neural-Network-Based Fault Classifier.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Functional Diagnosis for Graceful Degradation of NoC Switches.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
High-Throughput Logic Timing Simulation on GPGPUs.
ACM Trans. Design Autom. Electr. Syst., 2015

Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation.
ACM Trans. Design Autom. Electr. Syst., 2015

Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Fine-Grained Access Management in Reconfigurable Scan Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Adaptive multi-layer techniques for increased system dependability.
it Inf. Technol., 2015

Multi-Layer Test and Diagnosis for Dependable NoCs.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Efficient on-line fault-tolerance for the preconditioned conjugate gradient method.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Efficient observation point selection for aging monitoring.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Testing visions.
Proceedings of the 20th IEEE European Test Symposium, 2015

Low-overhead fault-tolerance for the preconditioned conjugate gradient solver.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

GPU-accelerated small delay fault simulation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

On-line prediction of NBTI-induced aging rates.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Intermittent and Transient Fault Diagnosis on Sparse Code Signatures.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

Optimized Selection of Frequencies for Faster-Than-at-Speed Test.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation.
ACM Trans. Design Autom. Electr. Syst., 2014

Exact Logic and Fault Simulation in Presence of Unknowns.
ACM Trans. Design Autom. Electr. Syst., 2014

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab., 2014

SAT-based ATPG beyond stuck-at fault testing.
it Inf. Technol., 2014

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems.
J. Electron. Test., 2014

Adaptive Bayesian Diagnosis of Intermittent Faults.
J. Electron. Test., 2014

Access Port Protection for Reconfigurable Scan Networks.
J. Electron. Test., 2014

Structural Software-Based Self-Test of Network-on-Chip.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Verifikation Rekonfigurierbarer Scan-Netze.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects.
Proceedings of the 2014 International Test Conference, 2014

Test pattern generation in presence of unknown values based on restricted symbolic logic.
Proceedings of the 2014 International Test Conference, 2014

Area-efficient synthesis of fault-secure NoC switches.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Data-parallel simulation for fast and accurate timing validation of CMOS circuits.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Incremental computation of delay fault detection probability for variation-aware test generation.
Proceedings of the 19th IEEE European Test Symposium, 2014

Variation-aware deterministic ATPG.
Proceedings of the 19th IEEE European Test Symposium, 2014

Diagnosis of multiple faults with highly compacted test responses.
Proceedings of the 19th IEEE European Test Symposium, 2014

A-ABFT: Autonomous Algorithm-Based Fault Tolerance for Matrix Multiplications on Graphics Processing Units.
Proceedings of the 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2014

Bit-Flipping Scan - A unified architecture for fault tolerance and offline test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Non-intrusive integration of advanced diagnosis features in automotive E/E-architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Adaptive parallel simulation of a two-timescale model for apoptotic receptor-clustering on GPUs.
Proceedings of the 2014 IEEE International Conference on Bioinformatics and Biomedicine, 2014

High Quality System Level Test and Diagnosis.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

On Covering Structural Defects in NoCs by Functional Tests.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Test Strategies for Reliable Runtime Reconfigurable Architectures.
IEEE Trans. Computers, 2013

Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures.
Proceedings of the 2013 IEEE International Test Conference, 2013

Efficacy and efficiency of algorithm-based fault-tolerance on GPUs.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Scan pattern retargeting and merging with reduced access time.
Proceedings of the 18th IEEE European Test Symposium, 2013

SAT-based code synthesis for fault-secure circuits.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Synthesis of workload monitors for on-line stress prediction.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Efficient variation-aware statistical dynamic timing analysis for delay test applications.
Proceedings of the Design, Automation and Test in Europe, 2013

Accurate QBF-based test pattern generation in presence of unknown values.
Proceedings of the Design, Automation and Test in Europe, 2013

Accurate Multi-cycle ATPG in Presence of X-Values.
Proceedings of the 22nd Asian Test Symposium, 2013

Securing Access to Reconfigurable Scan Networks.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Accurate X-Propagation for Test Applications by SAT-Based Reasoning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Structural Test and Diagnosis for Graceful Degradation of NoC Switches.
J. Electron. Test., 2012

A pseudo-dynamic comparator for error detection in fault tolerant architectures.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test.
Proceedings of the 13th Latin American Test Workshop, 2012

Modeling, verification and pattern generation for reconfigurable scan networks.
Proceedings of the 2012 IEEE International Test Conference, 2012

Transparent structural online test for reconfigurable systems.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Exact stuck-at fault classification in presence of unknowns.
Proceedings of the 17th IEEE European Test Symposium, 2012

Efficient system-level aging prediction.
Proceedings of the 17th IEEE European Test Symposium, 2012

Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test.
Proceedings of the 17th IEEE European Test Symposium, 2012

Parallel simulation of apoptotic receptor-clustering on GPGPU many-core architectures.
Proceedings of the 2012 IEEE International Conference on Bioinformatics and Biomedicine, 2012

Scan Test Power Simulation on GPGPUs.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Variation-Aware Fault Grading.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

Reuse of Structural Volume Test Methods for In-System Testing of Automotive ASICs.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware".
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
Variation-aware fault modeling.
Sci. China Inf. Sci., 2011

Efficient multi-level fault simulation of HW/SW systems for structural faults.
Sci. China Inf. Sci., 2011

P-PET: Partial pseudo-exhaustive test for high defect coverage.
Proceedings of the 2011 IEEE International Test Conference, 2011

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Soft error correction in embedded storage elements.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Fail-safety in core-based system design.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Towards Variation-Aware Test Methods.
Proceedings of the 16th European Test Symposium, 2011

Structural Test for Graceful Degradation of NoC Switches.
Proceedings of the 16th European Test Symposium, 2011

Structural In-Field Diagnosis for Random Logic Circuits.
Proceedings of the 16th European Test Symposium, 2011

SAT-based fault coverage evaluation in the presence of unknown values.
Proceedings of the Design, Automation and Test in Europe, 2011


A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Embedded Test for Highly Accurate Defect Localization.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Efficient BDD-based Fault Simulation in Presence of Unknown Values.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Diagnostic Test of Robust Circuits.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Algorithmen-basierte Fehlertoleranz für Many-Core-Architekturen (Algorithm-based Fault-Tolerance on Many-Core Architectures).
it Inf. Technol., 2010

Efficient Concurrent Self-Test with Partially Specified Patterns.
J. Electron. Test., 2010

Low-power test planning for arbitrary at-speed delay-test clock schemes.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Parity prediction synthesis for nano-electronic gate designs.
Proceedings of the 2011 IEEE International Test Conference, 2010

System reliability evaluation using concurrent multi-level simulation of structural faults.
Proceedings of the 2011 IEEE International Test Conference, 2010

Algorithm-based fault tolerance for many-core architectures.
Proceedings of the 15th European Test Symposium, 2010

Massive statistical process variations: A grand challenge for testing nanoelectronic circuits.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

BISD: Scan-based Built-In self-diagnosis.
Proceedings of the Design, Automation and Test in Europe, 2010

Efficient fault simulation on many-core processors.
Proceedings of the 47th Design Automation Conference, 2010

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

On Determining the Real Output Xs by SAT-Based Reasoning.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Adaptive Debug and Diagnosis Without Fault Dictionaries.
J. Electron. Test., 2009

Restrict Encoding for Mixed-Mode BIST.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead.
Proceedings of the 14th IEEE European Test Symposium, 2009

Test Encoding for Extreme Response Compaction.
Proceedings of the 14th IEEE European Test Symposium, 2009

Software-Based Hardware Fault Tolerance for Many-Core Architectures.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Test exploration and validation using transaction level models.
Proceedings of the Design, Automation and Test in Europe, 2009

A diagnosis algorithm for extreme space compaction.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Signature Rollback - A Technique for Testing Robust Circuits.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Integrating Scan Design and Soft Error Correction in Low-Power Applications.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Selective Hardening in Early Design Steps.
Proceedings of the 13th European Test Symposium, 2008

Test Set Stripping Limiting the Maximum Number of Specified Bits.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Scan Chain Organization for Embedded Diagnosis.
Proceedings of the Design, Automation and Test in Europe, 2008

Scan chain clustering for test power reduction.
Proceedings of the 45th Design Automation Conference, 2008

2007
Deterministic logic BIST for transition fault testing.
IET Comput. Digit. Tech., 2007

Programmable deterministic Built-In Self-Test.
Proceedings of the 2007 IEEE International Test Conference, 2007

Synthesis of irregular combinational functions with large don't care sets.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.
Proceedings of the 12th European Test Symposium, 2007

A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Scan Test Planning for Power Reduction.
Proceedings of the 44th Design Automation Conference, 2007

2006
X-masking during logic BIST and its impact on defect coverage.
IEEE Trans. Very Large Scale Integr. Syst., 2006

DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).
it Inf. Technol., 2006

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.
Proceedings of the IFIP VLSI-SoC 2006, 2006

BIST Power Reduction Using Scan-Chain Disable in the Cell Processor.
Proceedings of the 2006 IEEE International Test Conference, 2006

Some Common Aspects of Design Validation, Debug and Diagnosis.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Software-based self-test of processors under power constraints.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Implementing a Scheme for External Deterministic Self-Test.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Development of an audio player as system-on-a-chip using an open source platform.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschränkung.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

On the Reliability Evaluation of SRAM-Based FPGA Designs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

From embedded test to embedded diagnosis.
Proceedings of the 10th European Test Symposium, 2005

2004
Panel Summaries.
IEEE Des. Test Comput., 2004

X-Masking During Logic BIST and Its Impact on Defect Coverage.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Efficient Pattern Mapping for Deterministic Logic BIST.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Impact of Test Point Insertion on Silicon Area and Timing during Layout.
Proceedings of the 2004 Design, 2004

Reliability Considerations forMechatronic Systems on the Basis of a State Model.
Proceedings of the ARCS 2004, 2004

2003
Introduction.
ACM Trans. Design Autom. Electr. Syst., 2003

Test Engineering Education in Europe: the EuNICE-Test Project.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

2002
Efficient Online and Offline Testing of Embedded DRAMs.
IEEE Trans. Computers, 2002

A Mixed-Mode BIST Scheme Based on Folding Compression.
J. Comput. Sci. Technol., 2002

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.
J. Electron. Test., 2002

Reusing Scan Chains for Test Pattern Decompression.
J. Electron. Test., 2002

High Defect Coverage with Low-Power Test Sequences in a BIST Environment.
IEEE Des. Test Comput., 2002

Adapting an SoC to ATE Concurrent Test Capabilities.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Combining deterministic logic BIST with test point insertion.
Proceedings of the 7th European Test Workshop, 2002

RESPIN++ - deterministic embedded test.
Proceedings of the 7th European Test Workshop, 2002

2001
Application of Deterministic Logic BIST on Industrial Circuits.
J. Electron. Test., 2001

A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.
J. Electron. Test., 2001

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Tailoring ATPG for embedded testing.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Circuit partitioning for efficient logic BIST synthesis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Using mission logic for embedded testing.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

On applying the set covering model to reseeding.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Deterministic BIST with Partial Scan.
J. Electron. Test., 2000

Minimized Power Consumption for Scan-Based BIST.
J. Electron. Test., 2000

Non-intrusive BIST for systems-on-a-chip.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Optimal Hardware Pattern Generation for Functional BIST.
Proceedings of the 2000 Design, 2000

1999
Deterministic BIST with Multiple Scan Chains.
J. Electron. Test., 1999

Error Detecting Refreshment for Embedded DRAMs.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.
Proceedings of the Dependable Computing, 1999

Symmetric Transparent BIST for RAMs.
Proceedings of the 1999 Design, 1999

1998
Hardware-optimal test register insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

BIST for systems-on-a-chip.
Integr., 1998

Mixed-Mode BIST Using Embedded Processors.
J. Electron. Test., 1998

Synthesizing Fast, Online-Testable Control Units.
IEEE Des. Test Comput., 1998

Fast Self-Recovering Controllers.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Accumulator based deterministic BIST.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.
Proceedings of the 1998 Design, 1998

Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Guest Editorial.
J. Electron. Test., 1997

Power Dissipation During Testing: Should We Worry About it?
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Using BIST Control for Pattern Generation.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Fast controllers for data dominated applications.
Proceedings of the European Design and Test Conference, 1997

1996
Bit-flipping BIST.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Deterministic Pattern Generation for Weighted Random Pattern Testing.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Test register insertion with minimum hardware cost.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Pattern generation for a deterministic BIST scheme.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Synthesis of I/sub DDQ/-testable circuits: integrating built-in current sensors.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Configuring Flip-Flops to BIST Registers.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Simulation Results of an Efficient Defect-Analysis Procedure.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

An efficient procedure for the synthesis of fast self-testable controller structures.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Synthesis of Self-Testable Controllers.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1992
The pseudoexhaustive test of sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Optimized synthesis techniques for testable sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Prüfgerechter Entwurf und Test hochintegrierter Schaltungen.
Inform. Spektrum, 1992

1991
A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Emulation of Scan Paths in Sequential Circuit Synthesis.
Proceedings of the Fault-Tolerant Computing Systems, Tests, Diagnosis, 1991

Signature Analysis and Test Scheduling for Self-Testable Circuits.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

A Unified Approach for the Synthesis of Self-Testable Finite State Machines.
Proceedings of the 28th Design Automation Conference, 1991

1990
Multiple distributions for biased random test patterns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

An analytical approach to the partial scan problem.
J. Electron. Test., 1990

Error masking in self-testable circuits.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Generating pseudo-exhaustive vectors for external testing.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Optimized synthesis of self-testable finite state machines.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

The effectiveness of different test sets for PLAs.
Proceedings of the European Design Automation Conference, 1990

Tools and devices supporting the pseudo-exhaustive test.
Proceedings of the European Design Automation Conference, 1990

1989
The Pseudo-Exhaustive Test of Sequential Circuits.
Proceedings of the Proceedings International Test Conference 1989, 1989

The design of random-testable sequential circuits.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988
Automatisierung des Entwurfs vollständig testbarer Schaltungen.
Proceedings of the GI, 1988

Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987
On Computing Optimized Input Probabilities for Random Tests.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

Probabilistische Verfahren für den Test hochintegrierter Schaltungen
Informatik-Fachberichte 140, Springer, ISBN: 3-540-18072-9, 1987

1986
On fault modeling for dynamic MOS circuits.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
PROTEST: a tool for probabilistic testability analysis.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985


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