Michael E. Imhof

According to our database1, Michael E. Imhof authored at least 26 papers between 2007 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Fault tolerance infrastructure and its reuse for offline testing: synergies of a unified architecture to cope with soft errors and hard faults.
PhD thesis, 2015

High-Throughput Logic Timing Simulation on GPGPUs.
ACM Trans. Design Autom. Electr. Syst., 2015

2014
Structural Software-Based Self-Test of Network-on-Chip.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Variation-aware deterministic ATPG.
Proceedings of the 19th IEEE European Test Symposium, 2014

Bit-Flipping Scan - A unified architecture for fault tolerance and offline test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

On Covering Structural Defects in NoCs by Functional Tests.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Test Strategies for Reliable Runtime Reconfigurable Architectures.
IEEE Trans. Computers, 2013

Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures.
Proceedings of the 2013 IEEE International Test Conference, 2013

Synthesis of workload monitors for on-line stress prediction.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
A pseudo-dynamic comparator for error detection in fault tolerant architectures.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test.
Proceedings of the 13th Latin American Test Workshop, 2012

Transparent structural online test for reconfigurable systems.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

Variation-Aware Fault Grading.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware".
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
Efficient multi-level fault simulation of HW/SW systems for structural faults.
Sci. China Inf. Sci., 2011

P-PET: Partial pseudo-exhaustive test for high defect coverage.
Proceedings of the 2011 IEEE International Test Conference, 2011

Soft error correction in embedded storage elements.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Embedded Test for Highly Accurate Defect Localization.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
System reliability evaluation using concurrent multi-level simulation of structural faults.
Proceedings of the 2011 IEEE International Test Conference, 2010

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Test exploration and validation using transaction level models.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Integrating Scan Design and Soft Error Correction in Low-Power Applications.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Test Set Stripping Limiting the Maximum Number of Specified Bits.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Scan chain clustering for test power reduction.
Proceedings of the 45th Design Automation Conference, 2008

2007
Scan Test Planning for Power Reduction.
Proceedings of the 44th Design Automation Conference, 2007


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