Atefe Dalirsani

According to our database1, Atefe Dalirsani authored at least 12 papers between 2007 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2017
Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip.
IEEE Trans. Computers, 2017

2016
Functional Diagnosis for Graceful Degradation of NoC Switches.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Self-diagnosis in Network-on-Chips.
PhD thesis, 2015

Intermittent and Transient Fault Diagnosis on Sparse Code Signatures.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
Structural Software-Based Self-Test of Network-on-Chip.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Area-efficient synthesis of fault-secure NoC switches.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

On Covering Structural Defects in NoCs by Functional Tests.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
SAT-based code synthesis for fault-secure circuits.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012
Structural Test and Diagnosis for Graceful Degradation of NoC Switches.
J. Electron. Test., 2012

2011
Structural Test for Graceful Degradation of NoC Switches.
Proceedings of the 16th European Test Symposium, 2011

2007
An Analytical Model for Reliability Evaluation of NoC Architectures.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Using the inter- and intra-switch regularity in NoC switch testing.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007


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