Masahiko Ishiwaki

According to our database, Masahiko Ishiwaki authored at least 4 papers between 1997 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2002

A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology.

Tsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, Masahiko Ishiwaki

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000

14-bit 2.2-MS/s sigma-delta ADC's.

James C. Morizio, Michael Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh, Toshio Kumamoto, Takashi Okuda, Hiroshi Noda, Masahiko Ishiwaki, Takahiro Miki, Masao Nakaya

IEEE J. Solid State Circuits, 2000

SNDR sensitivity analysis for cascaded ΣΔ modulators.

James C. Morizio, Mike Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Mike Hood, Ward Huffman, Takashi Okuda, Hiroshi Noda, Yasuo Morimoto, Toshio Kumamoto, Masahiko Ishiwaki, Harufusa Kondoh, Masao Nakaya, Takahiro Miki

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1997

Scalable Shared-Buffering ATM Switch with a Versatile Searchable Queue.

Hideaki Yamanaka, Hirotaka Saito, Harofusa Kondoh, Yasuhito Sasaki, Hirotoshi Yamada, Munenori Tsuzuki, Satoshi Nishio, Hiromi Notani, Atsushi Iwabu, Masahiko Ishiwaki, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima

IEEE J. Sel. Areas Commun., 1997