Yoshio Matsuda

According to our database, Yoshio Matsuda authored at least 50 papers between 1989 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Users' Content Memorization in Multi-User Interactive Public Displays.

Narumi Sugiura, Rikako Ogura, Yoshio Matsuda, Takashi Komuro, Kayo Ogawa

Int. J. Hum. Comput. Interact., 2022

2020

Dynamic layout optimization for multi-user interaction with a large display.

Yoshio Matsuda, Takashi Komuro

Proceedings of the IUI '20: 25th International Conference on Intelligent User Interfaces, 2020

Palm-Controlled Pointing Interface Using a Dynamic Photometric Stereo Camera.

Yoshio Matsuda, Takashi Komuro, Takuya Yoda, Hajime Nagahara, Shoji Kawahito, Keiichiro Kagawa

Proceedings of the HCI International 2020 - Late Breaking Posters, 2020

2019

A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications.

Masanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka

IEICE Trans. Electron., 2019

Simultaneous interaction with a large display by many users.

Yuriko Sakakibara, Yoshio Matsuda, Takashi Komuro, Kayo Ogawa

Proceedings of the 8th ACM International Symposium on Pervasive Displays, PerDis 2019, 2019

Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis.

Kosuke Fukava, Kaito Mori, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura, Seiji Mochizuki

Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019

Scalable Architecture for High-Resolution Real-time Optical Flow Processor.

Kousuke Imamura, Satoshi Kanda, Saya Ohira, Yoshio Matsuda, Tetsuya Matsumura

Proceedings of the 2019 IEEE International Conference on Internet of Things and Intelligence System, 2019

2018

Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications.

Masanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai, Sugako Otani, Koji Nii, Yoshio Matsuda, Hiroyuki Kondo

IEEE Trans. Multi Scale Comput. Syst., 2018

High-Performance Super-Resolution via Patch-Based Deep Neural Network for Real-Time Implementation.

Reo Aoki, Kousuke Imamura, Akihiro Hirano, Yoshio Matsuda

IEICE Trans. Inf. Syst., 2018

A Multi-user Interactive Public Display with Dynamic Layout Optimization.

Yoshio Matsuda, Takashi Komuro

Proceedings of the 7th ACM International Symposium on Pervasive Displays, 2018

Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices.

Seiji Mochizuki, Kousuke Imamura, Kaito Mori, Yoshio Matsuda, Tetsuya Matsumura

Proceedings of the IEEE International Conference on Internet of Things and Intelligence System, 2018

2017

Design and Implementation of 176-MHz WXGA 30-fps Real-Time Optical Flow Processor.

Yu Suzuki, Masato Ito, Satoshi Kanda, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function.

Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals.

Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Automatic rule registration and deletion function on a packet lookup engine LSI.

Tetsuya Matsumura, Kousuke Imamura, Yoshifumi Kawamura, Yoshio Matsuda

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016

Image denoising using non-local means for Poisson noise.

Kousuke Imamura, Naoki Kimura, Fumiaki Satou, Shigeru Sanada, Yoshio Matsuda

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016

A study on fast motion estimation algorithm.

Masahiro Hiramori, Ryota Bandou, Shuhei Iwade, Hiroshi Makino, Tsutomu Yoshimura, Yoshio Matsuda

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

A study on motion estimation algorithm for moving pictures.

Ryota Bnadou, Masahiro Hiramori, Shuhei Iwade, Hiroshi Makino, Tutomu Yoshimura, Yoshio Matsuda

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

2015

A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table.

Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

A fast atom selection method based on the order of initial inner product values for image denoising using sparse representation.

Kousuke Imamura, Kaoru Itoh, Yoshio Matsuda

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

A Design for the 178-MHz WXGA 30-fps Optical Flow Processor Based on the HOE Algorithm.

Tetsuya Matsumura, Aoi Kurokawa, Kousuke Imamura, Yoshio Matsuda

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage.

Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, Yoshio Matsuda

IEEE Trans. Very Large Scale Integr. Syst., 2014

Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio.

Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current.

Shunji Nakata, Hiroshi Makino, Ryota Honda, Masayuki Miyama, Yoshio Matsuda

J. Circuits Syst. Comput., 2014

A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance.

Shunji Nakata, Hiroshi Makino, Yoshio Matsuda

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

The LSI implementation of a memory based field programmable device for MCU peripherals.

Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013

Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop.

Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.

Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology.

Shunji Nakata, Ryota Honda, Hiroshi Makino, Shin'ichiro Mutoh, Masayuki Miyama, Yoshio Matsuda

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield.

Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda

IET Circuits Devices Syst., 2012

Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current.

Shunji Nakata, Ryota Honda, Hiroshi Makino, Hiroki Morimura, Yoshio Matsuda

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

2011

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution.

Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda

IEEE Trans. Circuits Syst. II Express Briefs, 2011

Vehicle detection and tracking with affine motion segmentation in stereo video.

Masayuki Miyama, Yoshio Matsuda

Proceedings of the 2011 IEEE International Conference on Signal and Image Processing Applications, 2011

2010

Adiabatic charging and discharging method with minimum energy dissipation for a variable-gap capacitor system.

Shunji Nakata, Masayuki Miyama, Yoshio Matsuda

IET Circuits Devices Syst., 2010

A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation.

Yoshiki Yunbe, Masayuki Miyama, Yoshio Matsuda

IEICE Trans. Inf. Syst., 2010

A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications.

Katsumi Dosaka, Daisuke Ogawa, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda

IEICE Trans. Electron., 2010

Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation.

Shunji Nakata, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda

IEICE Electron. Express, 2010

Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit.

Shunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-power-line and Word-line Voltage.

Shunji Nakata, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition.

Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto

IEICE Trans. Electron., 2008

A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission.

Masayuki Miyama, Yuusuke Inoie, Takafumi Kasuga, Ryouichi Inada, Masashi Nakao, Yoshio Matsuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2000

A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology.

Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

Novel VLIW code compaction method for a 3D geometry processor.

Hiroaki Suzuki, Hiroshi Making, Yoshio Matsuda

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

The D30V/MPEG multimedia processor.

Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba

IEEE Micro, 1999

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface.

Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada

IEEE J. Solid State Circuits, 1999

1997

Scalable Shared-Buffering ATM Switch with a Versatile Searchable Queue.

Hideaki Yamanaka, Hirotaka Saito, Harofusa Kondoh, Yasuhito Sasaki, Hirotoshi Yamada, Munenori Tsuzuki, Satoshi Nishio, Hiromi Notani, Atsushi Iwabu, Masahiko Ishiwaki, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima

IEEE J. Sel. Areas Commun., 1997

1996

A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication.

Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi

IEEE J. Solid State Circuits, 1996

1994

Multicast Function and its LSI Implementation in a Shared Multibuffer ATM Switch.

Hirotaka Saito, Hideaki Yamanaka, Hirotoshi Yamada, Munenori Tsuzuki, Harofusa Kondoh, Yoshio Matsuda, Kazuyoshi Oshima

Proceedings of the Proceedings IEEE INFOCOM '94, 1994

1990

The cache DRAM architecture: a DRAM with an on-chip cache memory.

Hideto Hidaka, Yoshio Matsuda, Mikio Asakura, Kazuyasu Fujishima

IEEE Micro, 1990

1989

A New Array Architecture for Parallel Testing in VLSI Memories.

Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima

Proceedings of the Proceedings International Test Conference 1989, 1989