Harufusa Kondoh

According to our database, Harufusa Kondoh authored at least 4 papers between 1996 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2002

A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology.

Tsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, Masahiko Ishiwaki

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000

14-bit 2.2-MS/s sigma-delta ADC's.

James C. Morizio, Michael Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh, Toshio Kumamoto, Takashi Okuda, Hiroshi Noda, Masahiko Ishiwaki, Takahiro Miki, Masao Nakaya

IEEE J. Solid State Circuits, 2000

SNDR sensitivity analysis for cascaded ΣΔ modulators.

James C. Morizio, Mike Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Mike Hood, Ward Huffman, Takashi Okuda, Hiroshi Noda, Yasuo Morimoto, Toshio Kumamoto, Masahiko Ishiwaki, Harufusa Kondoh, Masao Nakaya, Takahiro Miki

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1996

A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication.

Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi

IEEE J. Solid State Circuits, 1996