Harufusa Kondoh

According to our database, Harufusa Kondoh authored at least 10 papers between 1991 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2002

A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology.

Tsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, Masahiko Ishiwaki

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000

14-bit 2.2-MS/s sigma-delta ADC's.

James C. Morizio, Michael Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Michael H. Hood, George Lynch, Harufusa Kondoh, Toshio Kumamoto, Takashi Okuda, Hiroshi Noda, Masahiko Ishiwaki, Takahiro Miki, Masao Nakaya

IEEE J. Solid State Circuits, 2000

SNDR sensitivity analysis for cascaded ΣΔ modulators.

James C. Morizio, Mike Hoke, Taskin Koçak, Clark Geddie, Chris Hughes, John Perry, Srinadh Madhavapeddi, Mike Hood, Ward Huffman, Takashi Okuda, Hiroshi Noda, Yasuo Morimoto, Toshio Kumamoto, Masahiko Ishiwaki, Harufusa Kondoh, Masao Nakaya, Takahiro Miki

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1997

Scalable Shared-Buffering ATM Switch with a Versatile Searchable Queue.

Hideaki Yamanaka, Hirotaka Saito, Harufusa Kondoh, Yasuhito Sasaki, Hirotoshi Yamada, Munenori Tsuzuki, Satoshi Nishio, Hiromi Notani, Atsushi Iwabu, Masahiko Ishiwaki, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima

IEEE J. Sel. Areas Commun., 1997

1996

A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication.

Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi

IEEE J. Solid State Circuits, 1996

1994

Multicast Function and its LSI Implementation in a Shared Multibuffer ATM Switch.

Hirotaka Saito, Hideaki Yamanaka, Hirotoshi Yamada, Munenori Tsuzuki, Harufusa Kondoh, Yoshio Matsuda, Kazuyoshi Oshima

Proceedings of the Proceedings IEEE INFOCOM '94, 1994

1993

A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture.

Harufusa Kondoh, Hiromi Notani, Hideaki Yamanaka, Keiichi Higashitani, Hirotaka Saito, Isamu Hayashi, Shigeki Kohama, Yoshio Matsuda, Kazuyoshi Oshima, Masao Nakaya

IEEE J. Solid State Circuits, July, 1993

1991

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture.

Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Hiromi Notani, Harufusa Kondoh, Shinpei Kayano

IEEE J. Solid State Circuits, November, 1991

A 10-b 70-MS/s CMOS D/A converter.

Yasuyuki Nakamura, Takahiro Miki, Atsushi Maeda, Harufusa Kondoh, Nobuharu Yazawa

IEEE J. Solid State Circuits, April, 1991

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses.

Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Harufusa Kondoh, Shimpei Kayano

IEEE J. Solid State Circuits, April, 1991