Kimio Ueda

According to our database, Kimio Ueda authored at least 4 papers between 1994 and 2002.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2002

A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology.

Tsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, Masahiko Ishiwaki

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000

A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology.

Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara

IEEE J. Solid State Circuits, 2000

1996

A fully compensated active pull-down ECL circuit with self-adjusting driving capability.

Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Koichiro Mashiko

IEEE J. Solid State Circuits, 1996

1994

A voltage compensated series-gate bipolar circuit operating at sub-2 V.

Hisayasu Sato, Kimio Ueda, Nagisa Sasaki, Tatsuhiko Ikeda, Koichiro Mashiko

IEEE J. Solid State Circuits, October, 1994