Masahiro Sowa

According to our database, Masahiro Sowa authored at least 40 papers between 1982 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory.

Duc-Hung Le, Katsumi Inoue, Masahiro Sowa, Cong-Kha Pham

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2010

Compiling for Reduced Bit-Width Queue Processors.

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa

J. Signal Process. Syst., 2010

2009

Compiler Support for Code Size Reduction Using a Queue-Based Processor.

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa

Trans. High Perform. Embed. Archit. Compil., 2009

Efficient compilation for queue size constrained queue processors.

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa

Parallel Comput., 2009

Design and implementation of a queue compiler.

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa

Microprocess. Microsystems, 2009

2008

Dual-execution mode processor architecture.

Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa

J. Supercomput., 2008

The QC-2 parallel Queue processor architecture.

Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa

J. Parallel Distributed Comput., 2008

A new code generation algorithm for 2-offset producer order queue computation model.

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa

Comput. Lang. Syst. Struct., 2008

Quantitative Evaluation of Common Subexpression Elimination on Queue Machines.

Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek

Proceedings of the 9th International Symposium on Parallel Architectures, 2008

2007

Dual-Execution Mode Processor Architecture For Embedded Applications.

Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa

J. Mobile Multimedia, 2007

Optimizing Reaching Definitions Overhead in Queue Processors.

Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa

J. Convergence Inf. Technol., 2007

Queue Register File Optimization Algorithm for QueueCore Processor.

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa

Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP.

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa

Proceedings of the Eighth International Conference on Parallel and Distributed Computing, 2007

Mathematical Model for Multiobjective Synthesis of NoC Architectures.

Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa

Proceedings of the 2007 International Conference on Parallel Processing Workshops (ICPP Workshops 2007), 2007

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model.

Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

2006

High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.

Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa

J. Supercomput., 2006

Design and architecture for an embedded 32-bit QueueCore.

Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa

J. Embed. Comput., 2006

On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation.

Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa

Proceedings of the Frontiers of High Performance Computing and Networking, 2006

Scalable Core-Based Methodology and Synthesizable Core for Systematic Design.

Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa

Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006

2005

Parallel Queue Processor Architecture Based on Produced Order Computation Model.

Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga

J. Supercomput., 2005

An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture.

Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa

Proceedings of the Embedded and Ubiquitous Computing, 2005

Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.

Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa

Proceedings of the Embedded and Ubiquitous Computing, 2005

2003

On the Design of a Register Queue Based Processor Architecture (FaRM-rq).

Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa

Proceedings of the Parallel and Distributed Processing and Applications, 2003

2002

Proposal and Design of a Parallel Queue Processor Architecture (PQP).

Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga

Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Compiler-Controlled Parallelism-Independent Scheduling for Parallel and Distributed Systems.

Kirilka Nikolova, Sou Pei You, Masahiro Sowa

Proceedings of the Applied Parallel Computing Advanced Scientific Computing, 2002

Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing Systems.

Kirilka Nikolova, Masahiro Sowa

Proceedings of the 16th Annual International Symposium on High Performance Computing Systems and Applications, 2002

2001

Access route control by an extended key/lock scheme.

Soichi Shigeta, Kentaro Shimizu, Masahiro Sowa

Comput. Syst. Sci. Eng., 2001

1997

Intruction Fetch Mechanism for PN-Superscalar.

Shusuke Okamoto, Masahiro Sowa

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997

Program Controlled Cache Memory on Parallel Computer.

Mitsuaki Nakasumi, Shusuke Okamoto, Masahiro Sowa

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997

1996

Hybrid Processor Based on VLIW and PN-Superscalar.

Shusuke Okamoto, Masahiro Sowa

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

1994

V++: An Instruction-Restructurable Processor Architecture.

Takaya Arita, Hiromitsu Takagi, Masahiro Sowa

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1993

A static processor-scheduling algorithm resistive to dynamic fluctuation of execution timing.

Hiromitsu Takagi, Takaya Arita, Masahiro Sowa

Syst. Comput. Jpn., 1993

1992

Delayed instruction execution on a long instruction word (LIW) computer.

Komei Kato, Takaya Arita, Masahiro Sowa

Syst. Comput. Jpn., 1992

Performance of the PN superscalar processor as estimated by simulation.

Takaya Arita, Hiroaki Ito, Masahiro Sowa

Syst. Comput. Jpn., 1992

1991

Parallel execution on the function-partitioned processor with multiple instruction streams.

Masahiro Sowa, Takaya Arita, Tadaaki Kawamura, Hiromitsu Takagi

Syst. Comput. Jpn., 1991

High Speed Synchronization for a Statically Scheduled Superscalar Processor.

Takaya Arita, Masahiro Sowa

Int. J. High Speed Comput., 1991

1987

Performance of a simulated dataflow computer DFNDR-2.

Masahiro Sowa, Akitoshi Kamimura

Syst. Comput. Jpn., 1987

A Method for Speeding up Serial Processing in Dataflow Computers by Means of a Program Counter.

Masahiro Sowa

Comput. J., 1987

1985

A Timed Petri Net Model and Simulation of a Dataflow Computer.

T. Smigelski, Tadao Murata, Masahiro Sowa

Proceedings of the International Workshop on Timed Petri Nets, 1985

1982

A Data Flow Computer Architecture with Program and Token Memories.

Masahiro Sowa, Tadao Murata

IEEE Trans. Computers, 1982