Masahiro Sowa

According to our database1, Masahiro Sowa authored at least 39 papers between 1982 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2012
An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory.
IEICE Transactions, 2012

2010
Compiling for Reduced Bit-Width Queue Processors.
Signal Processing Systems, 2010

2009
Compiler Support for Code Size Reduction Using a Queue-Based Processor.
Trans. HiPEAC, 2009

Efficient compilation for queue size constrained queue processors.
Parallel Comput., 2009

Design and implementation of a queue compiler.
Microprocess. Microsystems, 2009

2008
Dual-execution mode processor architecture.
The Journal of Supercomputing, 2008

The QC-2 parallel Queue processor architecture.
J. Parallel Distributed Comput., 2008

A new code generation algorithm for 2-offset producer order queue computation model.
Comput. Lang. Syst. Struct., 2008

Quantitative Evaluation of Common Subexpression Elimination on Queue Machines.
Proceedings of the 9th International Symposium on Parallel Architectures, 2008

2007
Dual-Execution Mode Processor Architecture For Embedded Applications.
J. Mobile Multimedia, 2007

Optimizing Reaching Definitions Overhead in Queue Processors.
JCIT, 2007

Queue Register File Optimization Algorithm for QueueCore Processor.
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP.
Proceedings of the Eighth International Conference on Parallel and Distributed Computing, 2007

Mathematical Model for Multiobjective Synthesis of NoC Architectures.
Proceedings of the 2007 International Conference on Parallel Processing Workshops (ICPP Workshops 2007), 2007

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

2006
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
The Journal of Supercomputing, 2006

Design and architecture for an embedded 32-bit QueueCore.
J. Embedded Computing, 2006

On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation.
Proceedings of the Frontiers of High Performance Computing and Networking, 2006

Scalable Core-Based Methodology and Synthesizable Core for Systematic Design.
Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006

2005
Parallel Queue Processor Architecture Based on Produced Order Computation Model.
The Journal of Supercomputing, 2005

An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.
Proceedings of the Embedded and Ubiquitous Computing, 2005

2003
On the Design of a Register Queue Based Processor Architecture (FaRM-rq).
Proceedings of the Parallel and Distributed Processing and Applications, 2003

2002
Proposal and Design of a Parallel Queue Processor Architecture (PQP).
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

Compiler-Controlled Parallelism-Independent Scheduling for Parallel and Distributed Systems.
Proceedings of the Applied Parallel Computing Advanced Scientific Computing, 2002

Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing Systems.
Proceedings of the 16th Annual International Symposium on High Performance Computing Systems and Applications, 2002

2001
Access route control by an extended key/lock scheme.
Comput. Syst. Sci. Eng., 2001

1997
Intruction Fetch Mechanism for PN-Superscalar.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997

Program Controlled Cache Memory on Parallel Computer.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997

1996
Hybrid Processor Based on VLIW and PN-Superscalar.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

1994
V++: An Instruction-Restructurable Processor Architecture.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1993
A static processor-scheduling algorithm resistive to dynamic fluctuation of execution timing.
Systems and Computers in Japan, 1993

1992
Delayed instruction execution on a long instruction word (LIW) computer.
Systems and Computers in Japan, 1992

Performance of the PN superscalar processor as estimated by simulation.
Systems and Computers in Japan, 1992

1991
Parallel execution on the function-partitioned processor with multiple instruction streams.
Systems and Computers in Japan, 1991

High Speed Synchronization for a Statically Scheduled Superscalar Processor.
International Journal of High Speed Computing, 1991

1987
Performance of a simulated dataflow computer DFNDR-2.
Systems and Computers in Japan, 1987

1985
A Timed Petri Net Model and Simulation of a Dataflow Computer.
Proceedings of the International Workshop on Timed Petri Nets, 1985

1982
A Data Flow Computer Architecture with Program and Token Memories.
IEEE Trans. Computers, 1982


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