Ben A. Abderazek
Orcid: 0000-0003-3432-0718Affiliations:
- University of Aizu, Japan
According to our database1,
Ben A. Abderazek
authored at least 96 papers
between 2002 and 2024.
Collaborative distances:
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Bibliography
2024
A Hybrid Clustered Approach for Enhanced Communication and Model Performance in Blockchain-Based Collaborative Learning.
IEEE Access, 2024
Robust Vehicle-to-Grid Energy Trading Method Based on Smart Forecast and Multi-Blockchain Network.
IEEE Access, 2024
2023
Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023
Fault-Tolerant Spiking Neural Network Mapping Algorithm and Architecture to 3D-NoC-Based Neuromorphic Systems.
IEEE Access, 2023
R-MaS3N: Robust Mapping of Spiking Neural Networks to 3D-NoC-Based Neuromorphic Systems for Enhanced Reliability.
IEEE Access, 2023
An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture.
IEEE Access, 2023
HeterGenMap: An Evolutionary Mapping Framework for Heterogeneous NoC-Based Neuromorphic Systems.
IEEE Access, 2023
Interlinked Chain Method for Blockchain-Based Collaborative Learning in Vehicular Networks.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Fault Recovery in Spiking Neural Networks Through Target and Selection of Faulty Neurons for 3D Spiking Neuromorphic Processors.
Proceedings of the 6th IEEE International Conference on Knowledge Innovation and Invention, 2023
Robust Client Selection Based Secure Collaborative Learning Algorithm for Pneumonia Detection.
Proceedings of the 6th IEEE International Conference on Knowledge Innovation and Invention, 2023
2022
MigSpike: A Migration Based Algorithms and Architecture for Scalable Robust Neuromorphic Systems.
IEEE Trans. Emerg. Top. Comput., 2022
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
A Robust Multi-Stage Power Consumption Prediction Method in a Semi-Decentralized Network of Electric Vehicles.
IEEE Access, 2022
V2GNet: Robust Blockchain-Based Energy Trading Method and Implementation in Vehicle-to-Grid Network.
IEEE Access, 2022
Proceedings of the 4th IEEE Global Conference on Life Sciences and Technologies, 2022
Training Spiking Autoencoders by Truncated BPTT under Trade-offs between Simulation Steps and Reconstruction Error.
Proceedings of the IEEE International Conference on Development and Learning, 2022
Efficient Pneumonia Detection Method and Implementation in Chest X-ray Images Based on a Neuromorphic Spiking Neural Network.
Proceedings of the Computational Collective Intelligence - 14th International Conference, 2022
Springer, ISBN: 978-3-030-92524-6, 2022
2021
On the Design of a Fault-Tolerant Scalable Three Dimensional NoC-Based Digital Neuromorphic System With On-Chip Learning.
IEEE Access, 2021
Energy-Efficient Spike-Based Scalable Architecture for Next-Generation Cognitive AI Computing Systems.
Proceedings of the Ubiquitous Networking - 7th International Symposium, 2021
Smart Energy Management System based on Reconfigurable AI Chip and Electrical Vehicles.
Proceedings of the IEEE International Conference on Big Data and Smart Computing, 2021
2020
TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Scalable Design Methodology and Online Algorithm for TSV-Cluster Defects Recovery in Highly Reliable 3D-NoC Systems.
IEEE Trans. Emerg. Top. Comput., 2020
Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism.
IEEE Trans. Emerg. Top. Comput., 2020
Soft-Error and Hard-fault Tolerant Architecture and Routing Algorithm for Reliable 3D-NoC Systems.
CoRR, 2020
CoRR, 2020
AEBIS: AI-Enabled Blockchain-Based Electric Vehicle Integration System for Power Management in Smart Grid Platform.
IEEE Access, 2020
A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip.
IEEE Access, 2020
A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems.
IEEE Access, 2020
Light-Weight Spiking Neuron Processing Core for Large-Scale 3D-NoC Based Spiking Neural Network Processing Systems.
Proceedings of the 2020 IEEE International Conference on Big Data and Smart Computing, 2020
2019
Analytical performance assessment and high-throughput low-latency spike routing algorithm for spiking neural network systems.
J. Supercomput., 2019
Comprehensive Analytic Performance Assessment and K-means based Multicast Routing Algorithm and Architecture for 3D-NoC of Spiking Neurons.
ACM J. Emerg. Technol. Comput. Syst., 2019
Fault-Tolerant Spike Routing Algorithm and Architecture for Three Dimensional NoC-Based Neuromorphic Systems.
IEEE Access, 2019
TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the International Conference on Internet of Things, 2019
A Low-latency Tree-based Multicast Spike Routing for Scalable Multicore Neuromorphic Chips.
Proceedings of the 9th International Conference on Information Systems and Technologies, 2019
Low-Latency K-Means Based Multicast Routing Algorithm and Architecture for Three Dimensional Spiking Neuromorphic Chips.
Proceedings of the IEEE International Conference on Big Data and Smart Computing, 2019
2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
J. Supercomput., 2018
Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro inspired Architecture in Hardware.
Proceedings of the 2018 IEEE International Conference on Big Data and Smart Computing, 2018
2017
A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Microring fault-resilient photonic network-on-chip for reliable high-performance many-core systems.
J. Supercomput., 2017
A low-overhead soft-hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems.
J. Supercomput., 2017
Int. J. Embed. Syst., 2017
Real-Time UAV Attitude Heading Reference System Using Extended Kalman Filter for Programmable SoC.
Proceedings of the 11th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2017
Springer, ISBN: 978-981-10-6091-5, 2017
2016
Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems.
J. Parallel Distributed Comput., 2016
Proceedings of the International Conference on IC Design and Technology, 2016
Proceedings of the Fourth International Symposium on Computing and Networking, 2016
Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems.
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems.
J. Supercomput., 2015
Proceedings of the 2015 IEEE International Conference on Systems, 2015
Hybrid Photonic NoC Based on Non-Blocking Photonic Switch and Light-Weight Electronic Router.
Proceedings of the 2015 IEEE International Conference on Systems, 2015
FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the IEEE 7th International Conference on Awareness Science and Technology, 2015
2014
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures.
J. Parallel Distributed Comput., 2014
Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014
2013
Atlantis Ambient and Pervasive Intelligence 7, Atlantis Press, ISBN: 978-94-91216-92-3, 2013
Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC).
J. Supercomput., 2013
Run-Time Monitoring Mechanism for Efficient Design of Application-Specific NoC Architectures in Multi/Manycore Era.
Proceedings of the Seventh International Conference on Complex, 2013
2012
LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012
ONoC-SPL: Customized Network-on-Chip (NoC) architecture and prototyping for data-intensive computation applications.
Proceedings of the 4th International Conference on Awareness Science and Technology, 2012
Proceedings of the 4th International Conference on Awareness Science and Technology, 2012
Proceedings of the Third International Conference on Networking and Computing, 2012
2011
Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.
J. Supercomput., 2011
2010
Atlantis Ambient and Pervasive Intelligence 3, Atlantis Press, ISBN: 978-94-91216-33-6, 2010
An Efficient Algorithm and Embedded Multicore Implementation of ECG Analysis in Multi-lead Electrocardiogram Records.
Proceedings of the 39th International Conference on Parallel Processing, 2010
Proceedings of the Fifth International Conference on Broadband and Wireless Computing, 2010
Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC.
Proceedings of the Fifth International Conference on Broadband and Wireless Computing, 2010
2009
Trans. High Perform. Embed. Archit. Compil., 2009
Parallel Comput., 2009
Software and Hardware Design Issues for Low Complexity High Performance Processor Architecture.
Proceedings of the ICPPW 2009, 2009
2008
J. Parallel Distributed Comput., 2008
Comput. Lang. Syst. Struct., 2008
Proceedings of the 9th International Symposium on Parallel Architectures, 2008
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008
Advanced Optimization and Design Issues of a 32-Bit Embedded Processor Based on Produced Order Queue Computation Model.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008
2007
J. Mobile Multimedia, 2007
J. Convergence Inf. Technol., 2007
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007
Proceedings of the Eighth International Conference on Parallel and Distributed Computing, 2007
Proceedings of the 2007 International Conference on Parallel Processing Workshops (ICPP Workshops 2007), 2007
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007
2006
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
J. Supercomput., 2006
On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation.
Proceedings of the Frontiers of High Performance Computing and Networking, 2006
Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006
2005
J. Supercomput., 2005
Proceedings of the Embedded and Ubiquitous Computing, 2005
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.
Proceedings of the Embedded and Ubiquitous Computing, 2005
2003
Proceedings of the Parallel and Distributed Processing and Applications, 2003
2002
Proposal and Design of a Parallel Queue Processor Architecture (PQP).
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002