Ben A. Abderazek

According to our database1, Ben A. Abderazek authored at least 63 papers between 2002 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Analytical performance assessment and high-throughput low-latency spike routing algorithm for spiking neural network systems.
The Journal of Supercomputing, 2019

Comprehensive Analytic Performance Assessment and K-means based Multicast Routing Algorithm and Architecture for 3D-NoC of Spiking Neurons.
JETC, 2019

Fault-Tolerant Spike Routing Algorithm and Architecture for Three Dimensional NoC-Based Neuromorphic Systems.
IEEE Access, 2019

TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Low-Latency K-Means Based Multicast Routing Algorithm and Architecture for Three Dimensional Spiking Neuromorphic Chips.
Proceedings of the IEEE International Conference on Big Data and Smart Computing, 2019

2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018
SAFT-PHENIC: a thermal-aware microring fault-resilient photonic NoC.
The Journal of Supercomputing, 2018

Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro inspired Architecture in Hardware.
Proceedings of the 2018 IEEE International Conference on Big Data and Smart Computing, 2018

2017
A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model.
IEEE Trans. VLSI Syst., 2017

Microring fault-resilient photonic network-on-chip for reliable high-performance many-core systems.
The Journal of Supercomputing, 2017

A low-overhead soft-hard fault-tolerant architecture, design and management scheme for reliable high-performance many-core 3D-NoC systems.
The Journal of Supercomputing, 2017

Architecture and design of real-time system for elderly health monitoring.
IJES, 2017

Advanced Multicore Systems-On-Chip - Architecture, On-Chip Network, Design
Springer, ISBN: 978-981-10-6091-5, 2017

2016
Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems.
J. Parallel Distrib. Comput., 2016

Soft-error resilient Network-on-Chip for safety-critical applications.
Proceedings of the International Conference on IC Design and Technology, 2016

A Power Estimation Method for Mesh-Based Photonic NoC Routing Algorithms.
Proceedings of the Fourth International Symposium on Computing and Networking, 2016

Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip Systems.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems.
The Journal of Supercomputing, 2015

On the Design of a Fault-Tolerant Photonic Network-on-Chip.
Proceedings of the 2015 IEEE International Conference on Systems, 2015

Hybrid Photonic NoC Based on Non-Blocking Photonic Switch and Light-Weight Electronic Router.
Proceedings of the 2015 IEEE International Conference on Systems, 2015

FTTDOR: Microring Fault-resilient Optical Router for Reliable Optical Network-on-Chip Systems.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Contention-Free Routing for Hybrid Photonic Mesh-Based Network-on-Chip Systems.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Soft-error resilient 3D Network-on-Chip router.
Proceedings of the IEEE 7th International Conference on Awareness Science and Technology, 2015

2014
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures.
J. Parallel Distrib. Comput., 2014

Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-Chip Systems.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

2013
Multicore Systems On-Chip: Practical Software/Hardware Design, Second Edition
Atlantis Ambient and Pervasive Intelligence 7, Atlantis Press, ISBN: 978-94-91216-92-3, 2013

Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC).
The Journal of Supercomputing, 2013

Run-Time Monitoring Mechanism for Efficient Design of Application-Specific NoC Architectures in Multi/Manycore Era.
Proceedings of the Seventh International Conference on Complex, 2013

2012
LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012

ONoC-SPL: Customized Network-on-Chip (NoC) architecture and prototyping for data-intensive computation applications.
Proceedings of the 4th International Conference on Awareness Science and Technology, 2012

Towards smart health monitoring system for elderly people.
Proceedings of the 4th International Conference on Awareness Science and Technology, 2012

Low-overhead Routing Algorithm for 3D Network-on-Chip.
Proceedings of the Third International Conference on Networking and Computing, 2012

2011
Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture.
The Journal of Supercomputing, 2011

2010
Multicore Systems On-Chip: Practical Software/Hardware Design
Atlantis Ambient and Pervasive Intelligence 3, Atlantis Press, ISBN: 978-94-91216-33-6, 2010

Compiling for Reduced Bit-Width Queue Processors.
Signal Processing Systems, 2010

An Efficient Algorithm and Embedded Multicore Implementation of ECG Analysis in Multi-lead Electrocardiogram Records.
Proceedings of the 39th International Conference on Parallel Processing, 2010

Advanced Design Issues for OASIS Network-on-Chip Architecture.
Proceedings of the Fifth International Conference on Broadband and Wireless Computing, 2010

Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC.
Proceedings of the Fifth International Conference on Broadband and Wireless Computing, 2010

2009
Compiler Support for Code Size Reduction Using a Queue-Based Processor.
Trans. HiPEAC, 2009

Efficient compilation for queue size constrained queue processors.
Parallel Computing, 2009

Design and implementation of a queue compiler.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

Software and Hardware Design Issues for Low Complexity High Performance Processor Architecture.
Proceedings of the ICPPW 2009, 2009

2008
Dual-execution mode processor architecture.
The Journal of Supercomputing, 2008

The QC-2 parallel Queue processor architecture.
J. Parallel Distrib. Comput., 2008

A new code generation algorithm for 2-offset producer order queue computation model.
Comput. Lang. Syst. Struct., 2008

Quantitative Evaluation of Common Subexpression Elimination on Queue Machines.
Proceedings of the 9th International Symposium on Parallel Architectures, 2008

Single Instruction Dual-Execution Model Processor Architecture.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

Advanced Optimization and Design Issues of a 32-Bit Embedded Processor Based on Produced Order Queue Computation Model.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

2007
Dual-Execution Mode Processor Architecture For Embedded Applications.
J. Mobile Multimedia, 2007

Optimizing Reaching Definitions Overhead in Queue Processors.
JCIT, 2007

Queue Register File Optimization Algorithm for QueueCore Processor.
Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP.
Proceedings of the Eighth International Conference on Parallel and Distributed Computing, 2007

Mathematical Model for Multiobjective Synthesis of NoC Architectures.
Proceedings of the 2007 International Conference on Parallel Processing Workshops (ICPP Workshops 2007), 2007

An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model.
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

2006
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
The Journal of Supercomputing, 2006

Design and architecture for an embedded 32-bit QueueCore.
J. Embedded Computing, 2006

On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation.
Proceedings of the Frontiers of High Performance Computing and Networking, 2006

Scalable Core-Based Methodology and Synthesizable Core for Systematic Design.
Proceedings of the 2006 International Conference on Parallel Processing Workshops (ICPP Workshops 2006), 2006

2005
Parallel Queue Processor Architecture Based on Produced Order Computation Model.
The Journal of Supercomputing, 2005

An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.
Proceedings of the Embedded and Ubiquitous Computing, 2005

2003
On the Design of a Register Queue Based Processor Architecture (FaRM-rq).
Proceedings of the Parallel and Distributed Processing and Applications, 2003

2002
Proposal and Design of a Parallel Queue Processor Architecture (PQP).
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002


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