Fumio Yuki

According to our database1, Fumio Yuki authored at least 18 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
A 100-Gbps 4-Lane Transceiver for 47-dB Loss Copper Cable in 28-nm CMOS.
IEEE Trans. Circuits Syst., 2020

2016
3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion.
IEEE J. Solid State Circuits, 2014

2013
Compact and power-efficient 100-Gbps CMOS-based transceiver.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

High-frequency circuit design for 25 Gb/s×4 optical transceiver.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link.
IEEE J. Solid State Circuits, 2011

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process.
IEEE J. Solid State Circuits, 2010

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 25 Gbps inductorless receiver front-end in 65-nm CMOS for serial links.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS.
IEEE J. Solid State Circuits, 2009

10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1<sup>st</sup>-order ΔΣ modulator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006
A Low-Power Write Driver for Hard Disk Drives.
IEICE Trans. Electron., 2006

2004
A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking.
IEEE J. Solid State Circuits, 2004


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