Massimo Ruo Roch

Orcid: 0000-0001-7313-8017

According to our database1, Massimo Ruo Roch authored at least 52 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Design of Pyrrole-Based Gate-Controlled Molecular Junctions Optimized for Single-Molecule Aflatoxin B1 Detection.
Sensors, February, 2023

A Low Cost Open Platform for Development and Performance Evaluation of IoT and IIoT Systems.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

2022
Hand Gestures Recognition for Human-Machine Interfaces: A Low-Power Bio-Inspired Armband.
IEEE Trans. Biomed. Circuits Syst., December, 2022

Hybrid-SIMD: A Modular and Reconfigurable Approach to Beyond von Neumann Computing.
IEEE Trans. Computers, 2022

Motion Analysis for Experimental Evaluation of an Event-Driven FES System.
IEEE Trans. Biomed. Circuits Syst., 2022

VirtLAB: A Low-Cost Platform for Electronics Lab Experiments.
Sensors, 2022

NLCMAP: A Framework for the Efficient Mapping of Non-Linear Convolutional Neural Networks on FPGA Accelerators.
Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

A Side Channel Attack Methodology Applied to Code-Based Post Quantum Cryptography.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

2021
Octantis: An Exploration Tool for Beyond von Neumann architectures.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Low Latency Protocols Investigation for Event-Driven Wireless Body Area Networks.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

Live Demonstration: Event-Driven Hand Gesture Recognition for Wearable Human-Machine Interface.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

A Low Cost Compact Output Amplifier for Multichannel Muscle Stimulation.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2021

2020
Low-Complexity Reconfigurable DCT-V Architecture.
IEEE Trans. Circuits Syst., 2020

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis.
Sensors, 2020

Data Processing and Information Classification - An In-Memory Approach.
Sensors, 2020

vrLab: A Virtual and Remote Low Cost Electronics Lab Platform.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2020

2019
Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World.
Future Internet, 2019

A Low-Power Embedded System for Real-Time sEMG based Event-Driven Gesture Recognition.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Live Demonstration: Low Power Embedded System for Event-Driven Hand Gesture Recognition.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT).
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

Bitmap Index: A Processing-in-Memory Reconfigurable Implementation.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

2018
MECA, the microelectronics cloud alliance.
Proceedings of the 2018 IEEE Global Engineering Education Conference, 2018

A Low Cost ALS and VLC Circuit for Solid State Lighting.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

2017
ToPoliNano: A CAD Tool for Nano Magnetic Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Work-in-progress: MicroElectronics Cloud Alliance.
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017

2016
Reconfigurable Systolic Array: From Architecture to Physical Design for NML.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Understanding CMOS Technology Through TAMTAMS Web.
IEEE Trans. Emerg. Top. Comput., 2016

2015
Feedbacks in QCA: A Quantitative Approach.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Process Variability and Electrostatic Analysis of Molecular QCA.
ACM J. Emerg. Technol. Comput. Syst., 2015

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures.
Integr., 2015

Logic-in-Memory: A Nano Magnet Logic Implementation.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
ToPoliNano: NanoMagnet Logic Circuits Design and Simulation.
Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Fault tolerant nanoarray circuits: Automatic design and verification.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

High Speed VLSI Architecture for Finding the First W Maximum/Minimum Values.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

Implementation of a Spread-Spectrum-Based Smart Lighting System on an Embedded Platform.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

A Framework for Network-On-Chip Comparison Based on OpenSPARC T2 Processor.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

2013
Biosequences analysis on NanoMagnet Logic.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012
Time-Frequency Analysis of the Endocavitarian Signal in Paroxysmal Atrial Fibrillation.
IEEE Trans. Biomed. Eng., 2012

2011
A NoC-based hybrid message-passing/shared-memory approach to CMP design.
Microprocess. Microsystems, 2011

2010
MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A Case Study for NoC-Based Homogeneous MPSoC Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2008
An Automotive CD-Player Electro-Mechanics Fault Simulation Using VHDL-AMS.
J. Electron. Test., 2008

2007
A methodology and a case-study for network-on-chip based MP-SoC architectures.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology.
Proceedings of the International Symposium on System-on-Chip, 2007

2000
A high accuracy-low complexity model for CMOS delays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 50 Mbit/s Iterative Turbo-Decoder.
Proceedings of the 2000 Design, 2000

1999
VLSI architectures for turbo codes.
IEEE Trans. Very Large Scale Integr. Syst., 1999

New 2 Gbit/s CMOS I/O pads.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998
A 500 MHz 2d-DWT VLSI processor.
Proceedings of the 9th European Signal Processing Conference, 1998


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