Massimo Ruo Roch

According to our database1, Massimo Ruo Roch authored at least 30 papers between 1998 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 





Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World.
Future Internet, 2019

MECA, the microelectronics cloud alliance.
Proceedings of the 2018 IEEE Global Engineering Education Conference, 2018

A Low Cost ALS and VLC Circuit for Solid State Lighting.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

ToPoliNano: A CAD Tool for Nano Magnetic Logic.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Work-in-progress: MicroElectronics Cloud Alliance.
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017

Reconfigurable Systolic Array: From Architecture to Physical Design for NML.
IEEE Trans. VLSI Syst., 2016

Understanding CMOS Technology Through TAMTAMS Web.
IEEE Trans. Emerging Topics Comput., 2016

Feedbacks in QCA: A Quantitative Approach.
IEEE Trans. VLSI Syst., 2015

Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT.
IEEE Trans. on Circuits and Systems, 2015

Process Variability and Electrostatic Analysis of Molecular QCA.
JETC, 2015

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures.
Integration, 2015

Logic-in-Memory: A Nano Magnet Logic Implementation.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

ToPoliNano: NanoMagnet Logic Circuits Design and Simulation.
Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Fault tolerant nanoarray circuits: Automatic design and verification.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

High Speed VLSI Architecture for Finding the First W Maximum/Minimum Values.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

Implementation of a Spread-Spectrum-Based Smart Lighting System on an Embedded Platform.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

A Framework for Network-On-Chip Comparison Based on OpenSPARC T2 Processor.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2014

Time-Frequency Analysis of the Endocavitarian Signal in Paroxysmal Atrial Fibrillation.
IEEE Trans. Biomed. Engineering, 2012

A NoC-based hybrid message-passing/shared-memory approach to CMP design.
Microprocessors and Microsystems - Embedded Hardware Design, 2011

MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture.
Proceedings of the Design, Automation and Test in Europe, 2010

A Case Study for NoC-Based Homogeneous MPSoC Architectures.
IEEE Trans. VLSI Syst., 2009

An Automotive CD-Player Electro-Mechanics Fault Simulation Using VHDL-AMS.
J. Electronic Testing, 2008

A methodology and a case-study for network-on-chip based MP-SoC architectures.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

A high accuracy-low complexity model for CMOS delays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 50 Mbit/s Iterative Turbo-Decoder.
Proceedings of the 2000 Design, 2000

VLSI architectures for turbo codes.
IEEE Trans. VLSI Syst., 1999

New 2 Gbit/s CMOS I/O pads.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

A 500 MHz 2d-DWT VLSI processor.
Proceedings of the 9th European Signal Processing Conference, 1998