Carlo Condo

Orcid: 0000-0002-3050-036X

According to our database1, Carlo Condo authored at least 72 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Promising DSP Techniques to Increase Long Haul Transmission Capacity.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

2022
A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Iterative Soft-Input Soft-Output Decoding with Ordered Reliability Bits GRAND.
Proceedings of the IEEE Globecom 2022 Workshops, 2022

2021
Input-Distribution-Aware Successive Cancellation List Decoding of Polar Codes.
IEEE Commun. Lett., 2021

Staircase codes with non-systematic polar codes.
CoRR, 2021

Design of Polar Codes in 5G New Radio.
IEEE Commun. Surv. Tutorials, 2021

Fast-SCAN decoding of Polar Codes.
Proceedings of the 11th International Symposium on Topics in Coding, 2021

Input-distribution-aware parallel decoding of block codes.
Proceedings of the 11th International Symposium on Topics in Coding, 2021

Sliding Window Polar Codes.
Proceedings of the IEEE International Symposium on Information Theory, 2021

High-performance low-complexity error pattern generation for ORBGRAND decoding.
Proceedings of the IEEE Globecom 2021 Workshops, Madrid, Spain, December 7-11, 2021, 2021

2020
Practical Product Code Construction of Polar Codes.
IEEE Trans. Signal Process., 2020

High-Throughput Low-Latency Encoder and Decoder for a Class of Generalized Reed-Solomon Codes for Short-Reach Optical Communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Fast and Efficient Convolutional Accelerator for Edge Computing.
IEEE Trans. Computers, 2020

Minimum-effort successive cancellation list decoding of polar codes.
CoRR, 2020

Sliding Window Polar Codes.
CoRR, 2020

On List Decoding of 5G-NR Polar Codes.
Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020

Staircase Construction with Non-Systematic Polar Codes.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

SCAN List Decoding of Polar Codes.
Proceedings of the 2020 IEEE International Conference on Communications, 2020

2019
Operation Merging for Hardware Implementations of Fast Polar Decoders.
J. Signal Process. Syst., 2019

Rate-Flexible Fast Polar Decoders.
IEEE Trans. Signal Process., 2019

Improved Bit-Flipping Algorithm for Successive Cancellation Decoding of Polar Codes.
IEEE Trans. Commun., 2019

Design and Implementation of a Polar Codes Blind Detection Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Construction and Decoding of Product Codes with Non-Systematic Polar Codes.
Proceedings of the 2019 IEEE Wireless Communications and Networking Conference, 2019

SC-Flip Decoding of Polar Codes with High Order Error Correction Based on Error Dependency.
Proceedings of the 2019 IEEE Information Theory Workshop, 2019

Improved Hybrid Design of Polar Codes and Multi-Kernel Polar Codes.
Proceedings of the IEEE International Symposium on Information Theory, 2019

2018
Decoder Partitioning: Towards Practical List Decoding of Polar Codes.
IEEE Trans. Commun., 2018

A Multi-Kernel Multi-Code Polar Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

An Architecture to Accelerate Convolution in Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Improved successive cancellation flip decoding of polar codes based on error distribution.
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference Workshops, 2018

Efficient Operation Scheduling in Successive-Cancellation-based polar decoders.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

A Multi-Mode Accelerator for Pruned Deep Neural Networks.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Low-Complexity Software Stack Decoding of Polar Codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Convolutional Accelerator for Neural Networks With Binary Weights.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Partitioned Successive-Cancellation Flip Decoding of Polar Codes.
Proceedings of the 2018 IEEE International Conference on Communications, 2018

Generalized Fast Decoding of Polar Codes.
Proceedings of the IEEE Global Communications Conference, 2018

Memory Management in Successive-Cancellation based Decoders for Multi-Kernel Polar Codes.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
Fast and Flexible Successive-Cancellation List Decoders for Polar Codes.
IEEE Trans. Signal Process., 2017

Implementation of Sparse Superposition Codes.
IEEE Trans. Signal Process., 2017

Blind Detection With Polar Codes.
IEEE Commun. Lett., 2017

Memory-Efficient Polar Decoders.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

Multi-Mode Inference Engine for Convolutional Neural Networks.
CoRR, 2017

Fast Simplified Successive-Cancellation List Decoding of Polar Codes.
Proceedings of the 2017 IEEE Wireless Communications and Networking Conference Workshops, 2017

Reduced-memory high-throughput fast-SSC polar code decoder architecture.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Efficient bit-channel reliability computation for multi-mode polar code encoders and decoders.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks.
Proceedings of the 5th International Conference on Learning Representations, 2017

Activation pruning of deep convolutional neural networks.
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017

On error-correction performance and implementation of polar code list decoders for 5G.
Proceedings of the 55th Annual Allerton Conference on Communication, 2017

On the performance of polar codes for 5G eMBB control channel.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
A Fast Polar Code List Decoder Architecture Based on Sphere Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 9.96 dB NCG FEC scheme and 164 bits/cycle low-complexity product decoder architecture.
CoRR, 2016

Simplified Successive-Cancellation List decoding of polar codes.
Proceedings of the IEEE International Symposium on Information Theory, 2016

Matrix reordering for efficient list sphere decoding of polar codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Stall pattern avoidance in polynomial product codes.
Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016

2015
VLSI decoding architectures: flexibility, robustness and performance.
PhD thesis, 2015

Unequal Error Protection of Memories in LDPC Decoders.
IEEE Trans. Computers, 2015

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures.
Integr., 2015

Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders.
Circuits Syst. Signal Process., 2015

Sparse superposition codes: A practical approach.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

List sphere decoding of polar codes.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Unified turbo/LDPC code decoder architecture for deep-space communications.
IEEE Trans. Aerosp. Electron. Syst., 2014

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced.
IEEE Signal Process. Lett., 2014

Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding.
IET Commun., 2014

A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors.
IEEE Embed. Syst. Lett., 2014

Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014

2013
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Flexible LDPC Decoder Architectures.
VLSI Design, 2012

A Network-on-Chip-based turbo/LDPC decoder architecture.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture
CoRR, 2011

A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011


  Loading...