Gianluca Piccinini

According to our database1, Gianluca Piccinini authored at least 38 papers between 1987 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Nanoarrays for Systolic Biosequence Analysis.
Journal of Circuits, Systems, and Computers, 2018

2015
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT.
IEEE Trans. on Circuits and Systems, 2015

Process Variability and Electrostatic Analysis of Molecular QCA.
JETC, 2015

2014
Understanding a Bisferrocene Molecular QCA Wire.
Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values.
IEEE Trans. on Circuits and Systems, 2014

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced.
IEEE Signal Process. Lett., 2014

Molecular transistor circuits: From device model to circuit simulation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

2013
Charge distribution in a molecular QCA wire based on bis-ferrocene molecules.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Nanogap-based enzymatic-free electrochemical detection of glucose.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012
UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2.
IEEE Trans. VLSI Syst., 2012

2010
Scalable low-complexity B-spline discrete wavelet transform architecture.
IET Circuits, Devices & Systems, 2010

2008
Statistical power supply dynamic noise prediction in hierarchical power grid and package networks.
Integration, 2008

2004
An electromigration and thermal model of power wires for a priori high-level reliability prediction.
IEEE Trans. VLSI Syst., 2004

Effects of temperature in deep-submicron global interconnect optimization in future technology nodes.
Microelectronics Journal, 2004

2003
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations.
VLSI Signal Processing, 2003

Coupled electro-thermal modeling and optimization of clock networks.
Microelectronics Journal, 2003

Effects of Temperature in Deep-Submicron Global Interconnect Optimization.
Proceedings of the Integrated Circuit and System Design, 2003

A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.
Proceedings of the Integrated Circuit and System Design, 2003

Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002
Architectural strategies for low-power VLSI turbo decoders.
IEEE Trans. VLSI Syst., 2002

Clock Distribution Network Optimization under Self-Heating and Timing Constraints.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Reconfigurable DSP IP for multimedia applications.
Proceedings of the IEEE International Conference on Acoustics, 2002

Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Switching Noise Analysis Framework For High Speed Logic Families.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Hierarchical power supply noise evaluation for early power grid design prediction.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Synthesis of low-leakage PD-SOI circuits with body-biasing.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Noise Safety Design Methodologies.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

A high accuracy-low complexity model for CMOS delays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 50 Mbit/s Iterative Turbo-Decoder.
Proceedings of the 2000 Design, 2000

1999
VLSI architectures for turbo codes.
IEEE Trans. VLSI Syst., 1999

New 2 Gbit/s CMOS I/O pads.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998
Fanout optimization under a submicron transistor-level delay model.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

A 500 MHz 2d-DWT VLSI processor.
Proceedings of the 9th European Signal Processing Conference, 1998

1996
A 650 MHz pipelined MAC for DSP applications using a new clocking strategy.
Proceedings of the 8th European Signal Processing Conference, 1996

1992
Deflection network: Principles, implementation, services.
European Transactions on Telecommunications, 1992

1989
Implementation studies for a VLSI Prolog coprocessor.
IEEE Micro, 1989

1987
An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results.
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987


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