Gianluca Piccinini

Orcid: 0000-0002-9385-6195

According to our database1, Gianluca Piccinini authored at least 52 papers between 1987 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Design of Pyrrole-Based Gate-Controlled Molecular Junctions Optimized for Single-Molecule Aflatoxin B1 Detection.
Sensors, February, 2023

Taming Molecular Field-Coupling for Nanocomputing Design.
ACM J. Emerg. Technol. Comput. Syst., January, 2023

Advances in Modeling of Noisy Quantum Computers: Spin Qubits in Semiconductor Quantum Dots.
IEEE Access, 2023

2021
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Reconfigurable Field-Coupled Nanocomputing Paradigm on Uniform Molecular Monolayers.
Proceedings of the 2021 International Conference on Rebooting Computing (ICRC), Los Alamitos, CA, USA, November 30, 2021

2020
SCERPA: A Self-Consistent Algorithm for the Evaluation of the Information Propagation in Molecular Field-Coupled Nanocomputing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
Bistable Propagation of Monostable Molecules in Molecular Field-Coupled Nanocomputing.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

2018
Nanoarrays for Systolic Biosequence Analysis.
J. Circuits Syst. Comput., 2018

2015
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Process Variability and Electrostatic Analysis of Molecular QCA.
ACM J. Emerg. Technol. Comput. Syst., 2015

2014
Understanding a Bisferrocene Molecular QCA Wire.
Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced.
IEEE Signal Process. Lett., 2014

Molecular transistor circuits: From device model to circuit simulation.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

2013
Charge distribution in a molecular QCA wire based on bis-ferrocene molecules.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Nanogap-based enzymatic-free electrochemical detection of glucose.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012
UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2010
Scalable low-complexity B-spline discrete wavelet transform architecture.
IET Circuits Devices Syst., 2010

2008
Statistical power supply dynamic noise prediction in hierarchical power grid and package networks.
Integr., 2008

2004
An electromigration and thermal model of power wires for a priori high-level reliability prediction.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Effects of temperature in deep-submicron global interconnect optimization in future technology nodes.
Microelectron. J., 2004

2003
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations.
J. VLSI Signal Process., 2003

Coupled electro-thermal modeling and optimization of clock networks.
Microelectron. J., 2003

Effects of Temperature in Deep-Submicron Global Interconnect Optimization.
Proceedings of the Integrated Circuit and System Design, 2003

A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.
Proceedings of the Integrated Circuit and System Design, 2003

Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002
Architectural strategies for low-power VLSI turbo decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Clock Distribution Network Optimization under Self-Heating and Timing Constraints.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Embedded IWT evaluation in reconfigurable wireless sensor network.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

System architecture for error-resilient, embedded JPEG2000 wireless delivery.
Proceedings of the 14th International Conference on Digital Signal Processing, 2002

Reconfigurable DSP IP for multimedia applications.
Proceedings of the IEEE International Conference on Acoustics, 2002

Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Switching Noise Analysis Framework For High Speed Logic Families.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Hierarchical power supply noise evaluation for early power grid design prediction.
Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Synthesis of low-leakage PD-SOI circuits with body-biasing.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Reconfigurable coprocessor based JPEG 2000 implementation.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

JPEG 2000: finite precision representation and hardware implications.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Noise Safety Design Methodologies.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

A high accuracy-low complexity model for CMOS delays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 50 Mbit/s Iterative Turbo-Decoder.
Proceedings of the 2000 Design, 2000

1999
VLSI architectures for turbo codes.
IEEE Trans. Very Large Scale Integr. Syst., 1999

A global optimization tool for CMOS logic circuits.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

New 2 Gbit/s CMOS I/O pads.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code.
Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998
Fanout optimization under a submicron transistor-level delay model.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

A 500 MHz 2d-DWT VLSI processor.
Proceedings of the 9th European Signal Processing Conference, 1998

1997
A comprehensive submicrometer MOST delay model and its application to CMOS buffers.
IEEE J. Solid State Circuits, 1997

1996
A 650 MHz pipelined MAC for DSP applications using a new clocking strategy.
Proceedings of the 8th European Signal Processing Conference, 1996

1992
Deflection network: Principles, implementation, services.
Eur. Trans. Telecommun., 1992

1989
Implementation studies for a VLSI Prolog coprocessor.
IEEE Micro, 1989

1987
Design considerations on a VLSI Prolog interpreter.
Microprocess. Microprogramming, 1987

An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results.
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987


  Loading...