Matthieu Tuna

According to our database, Matthieu Tuna authored at least 10 papers between 2004 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Multi-FPGA prototyping board issue: the FPGA I/O bottleneck.

Qingshan Tang, Habib Mehrez, Matthieu Tuna

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only).

Qingshan Tang, Matthieu Tuna, Habib Mehrez

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling, and Custom.

Qingshan Tang, Matthieu Tuna, Habib Mehrez

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013

Routing algorithm for multi-FPGA based systems using multi-point physical tracks.

Qingshan Tang, Matthieu Tuna, Habib Mehrez

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist.

Qingshan Tang, Matthieu Tuna, Zied Marrakchi, Habib Mehrez

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA board.

Qingshan Tang, Habib Mehrez, Matthieu Tuna

Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

A logic sharing synthesis tool for mutually exclusive applications.

Alp Kiliç, Zied Marrakchi, Matthieu Tuna, Habib Mehrez

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

2007

At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester.

Matthieu Tuna, Mounir Benabdenbi, Alain Greiner

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

2004

High Level Synthesis Methodology from C to FPGA Used for a Network Protocol Communication.

M. Diaby, Matthieu Tuna, Jean Lou Desbarbieux, Franck Wajsbürt

Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores.

Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna

Proceedings of the 2004 Design, 2004