Mounir Benabdenbi

According to our database, Mounir Benabdenbi authored at least 32 papers between 2000 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

FPU Reduced Variable Precision in Time: Application to the Jacobi Iterative Method.

Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020

FPU Bit-Width Optimization for Approximate Computing: A Non-Intrusive Approach.

Noureddine Ait Said, Mounir Benabdenbi, Katell Morin-Allory

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

2019

On-Line Adjustable Precision Computing.

Ali Skaf, Mona Ezzadeen, Mounir Benabdenbi, Laurent Fesquet

Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

2018

Test and Reliability in Approximate Computing.

Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena Ioana Vatajelu

J. Electron. Test., 2018

2015

Application-independent testing of multilevel interconnect in mesh-based FPGAs.

Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014

On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures.

Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux

IEEE Trans. Very Large Scale Integr. Syst., 2014

Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip.

Michael G. Dimopoulos, Yi Gang, Lorena Anghel, Mounir Benabdenbi, Nacer-Eddine Zergainoh, Michael Nicolaidis

Microprocess. Microsystems, 2014

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA.

Saif-Ur Rehman, Adrien Blanchardon, Arwa Ben Dhia, Mounir Benabdenbi, Roselyne Chotin-Avot, Lirida A. B. Naviner, Lorena Anghel, Habib Mehrez, Emna Amouri, Zied Marrakchi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Cost-efficient of a cluster in a mesh SRAM-based FPGA.

Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

System on chip project: Integration of a Motion-JPEG video decoder.

Lorena Anghel, Mounir Benabdenbi, Frédéric Pétrot

Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

2013

Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip.

Michael G. Dimopoulos, Yi Gang, Mounir Benabdenbi, Lorena Anghel, Nacer-Eddine Zergainoh, Michael Nicolaidis

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

A defect-tolerant cluster in a mesh SRAM-based FPGA.

Arwa Ben Dhia, Saif-Ur Rehman, Adrien Blanchardon, Lirida A. B. Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez, Zied Marrakchi

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

BIST for logic and local interconnect resources in a novel mesh of cluster FPGA.

Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems.

Vladimir Pasca, Lorena Anghel, Michael Nicolaidis, Mounir Benabdenbi

J. Electron. Test., 2012

Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis.

Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi

J. Electron. Test., 2012

Efficient link-level error resilience in 3D NoCs.

Vladimir Pasca, Saif-Ur Rehman, Lorena Anghel, Mounir Benabdenbi

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

Localization of damaged resources in NoC based shared-memory MP2SOC, using a Distributed Cooperative Configuration Infrastructure.

Zhen Zhang, Dimitri Refauvelet, Alain Greiner, Mounir Benabdenbi, François Pêcheux

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Configurable Thru-Silicon-Via interconnect Built-In Self-Test and diagnosis.

Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi

Proceedings of the 12th Latin American Test Workshop, 2011

2010

Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components.

Zhen Zhang, Alain Greiner, Mounir Benabdenbi

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Configurable serial fault-tolerant link for communication in 3D integrated systems.

Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Distributed online software monitoring of manycore architectures.

Etienne Faure, Mounir Benabdenbi, François Pêcheux

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Configurable fault-tolerant link for inter-die communication in 3D on-chip networks.

Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi

Proceedings of the 15th European Test Symposium, 2010

Fault tolerant communication in 3D integrated systems.

Vladimir Pasca, Lorena Anghel, Mounir Benabdenbi

Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

An in-memory monitoring database for self adaptive MP²SoCs.

Etienne Faure, Gabriel Marchesan Almeida, Mounir Benabdenbi, Pascal Benoit, Fabien Clermidy, François Pêcheux, Gilles Sassatelli, Lionel Torres

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2009

On-line test and monitoring of multi-processor SoCs: A software-based approach.

Mounir Benabdenbi, François Pêcheux, Etienne Faure

Proceedings of the 10th Latin American Test Workshop, 2009

2007

At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester.

Matthieu Tuna, Mounir Benabdenbi, Alain Greiner

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

2006

MP-SoC Architecture for an Obstacle Detection Application in Pre-Crash Situation.

Alain Greiner, Frédéric Pétrot, M. Carrier, Mounir Benabdenbi, Roselyne Chotin-Avot, Raphaël Labayrade

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

2004

STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores.

Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna

Proceedings of the 2004 Design, 2004

2002

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing.

Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

J. Electron. Test., 2002

2001

Testing TAPed cores and wrapped cores with the same test access mechanism.

Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Solving the I/O Bandwidth Problem in System on a Chip Testing.

Walid Maroufi, Mounir Benabdenbi, Meryem Marzouki

Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip.

Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki

Proceedings of the 2000 Design, 2000