Mely Chen Chi

According to our database1, Mely Chen Chi authored at least 13 papers between 1987 and 2012.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2012
A 3D IC designs partitioning algorithm with power consideration.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

NBTI-aware dual threshold voltage assignment for leakage power reduction.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A layer prediction method for minimum cost three dimensional integrated circuits.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010
A multilevel multilayer partitioning algorithm for three dimensional integrated circuits.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2007
Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2005
A Wide-Swing V_T-Referenced Circuit with Insensitivity to Device Mismatch.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

An IR drop-driven placer for standard cells in a SOC design.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

2004
Micro-power low-offset instrumentation amplifier IC design for biomedical system applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Low-power driven standard-cell placement based on a multilevel force-directed algorithm.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

2003
A 0.75-mW analog processor IC for wireless biosignal monitor.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2000
A Reliable Clock Tree Design Methodology for ASIC Designs.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1987
An Automatic Rectilinear Partitioning Procedure for Standard Cells.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987


  Loading...