Wen-Pin Tu

According to our database, Wen-Pin Tu authored at least 12 papers between 2008 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol.

Hua-Hsin Yeh, Wen-Pin Tu, Jian-Zhi Shen, Tung-Hua Yen, Shih-Hsu Huang

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew.

Tsung-Tang Lin, Wen-Pin Tu, Shih-Hsu Huang

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Low-power anti-aging zero skew clock gating.

Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang, Song-Bin Pan

ACM Trans. Design Autom. Electr. Syst., 2013

Low-power timing closure methodology for ultra-low voltage designs.

Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Co-synthesis of data paths and clock control paths for minimum-period clock gating.

Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng

Proceedings of the Design, Automation and Test in Europe, 2013

2012

High-Level Synthesis for Minimum-Area Low-Power Clock Gating.

Shih-Hsu Huang, Wen-Pin Tu, Bing-Hung Li

J. Inf. Sci. Eng., 2012

NBTI-aware dual threshold voltage assignment for leakage power reduction.

Wen-Pin Tu, Shih-Wei Wu, Shih-Hsu Huang, Mely Chen Chi

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits.

Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

TSV sharing through multiplexing for TSV count minimization in high-level synthesis.

Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Teaching three-dimensional system-in-package design automation in a semester course.

Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, Chun-Hua Cheng

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

2010

Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating.

Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2008

Module binding for low power clock gating.

Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu

IEICE Electron. Express, 2008