Shih-Hsu Huang

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

Fault-Tolerant Near-Memory MAC Design with Redundant Memories.

[BibT_eX]

[DOI]

Hsin-Chen Lu

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

An Automatic Facial Analysis System for The Detection of Pediatric Obstructive Sleep Apnea.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

Hardware Trojans of Computing-In-Memories: Issues and Methods.

[BibT_eX]

[DOI]

Wei-Che Cheng

Jin-Fu Li

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022

Dataflow and Hardware Design for The Sharing of Feature Maps.

[BibT_eX]

[DOI]

De-Yang Chiu

Proceedings of the 19th International SoC Design Conference, 2022

Design and Dataflow for Multibit SRAM-Based MAC Operations.

[BibT_eX]

[DOI]

Chuan-Han Cheng

Jin-Fu Li

Proceedings of the 19th International SoC Design Conference, 2022

A Reinforcement Learning Methodology for The Search of SRAM CIM-based Accelerator Configuration.

[BibT_eX]

[DOI]

Bo-Xi Lai

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022

Network Pruning by Feature Map Sharing with K-Means Clustering.

[BibT_eX]

[DOI]

De-Yang Chiu

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022

A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Block-Based Compression and Corresponding Hardware Circuits for Sparse Activations.

[BibT_eX]

[DOI]

Yui-Kai Weng

Sensors, 2021

Convolver Design and Convolve-Accumulate Unit Design for Low-Power Edge Computing.

[BibT_eX]

[DOI]

Xin-Jia Chen

Sensors, 2021

ECO Timing Optimization with Data Paths and Clock Paths Considered.

[BibT_eX]

[DOI]

Jia-Xiang Tang

Jui-Hung Hung

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

Hybrid Dynamic Fixed Point Quantization Methodology for AI Accelerators.

[BibT_eX]

[DOI]

Wei-Hung Lin

Proceedings of the 18th International SoC Design Conference, 2021

Low-Power Low-Error Fixed-Width Multiplier Design for Digital Signal Processing.

[BibT_eX]

[DOI]

En-Hui Zhang

Proceedings of the IEEE International Conference on Consumer Electronics, 2021

Block-Based Compression for Reducing Indexing Cost of DNN Accelerators.

[BibT_eX]

[DOI]

Yui-Kai Weng

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

Hardware Implementation for Fending off Side-Channel Attacks.

[BibT_eX]

[DOI]

Yi-Liang Hong

Yui-Kai Weng

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

2020

A High-Performance Multiply-Accumulate Unit by Integrating Additions and Accumulations Into Partial Product Reduction Process.

[BibT_eX]

[DOI]

Che-Wei Tung

IEEE Access, 2020

Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

A Simple Yet Accurate Method for The Unsigned Fixed-Width Multiplier Design.

[BibT_eX]

[DOI]

En-Hui Zhang

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

Low-Power Hardware Implementation for Parametric Rectified Linear Unit Function.

[BibT_eX]

[DOI]

Yu-Hsuan Wu

Wei-Hung Lin

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

Low-Power Hardware Architecture for Depthwise Separable Convolution Unit Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

Low-Power Small-Area $3\times 3$ Convolution Hardware Design.

[BibT_eX]

[DOI]

Xin-Jia Chen

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019

A Design Framework for Hardware Approximation of Deep Neural Networks.

[BibT_eX]

[DOI]

Wei-Hung Lin

Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019

Softsign Function Hardware Implementation Using Piecewise Linear Approximation.

[BibT_eX]

[DOI]

Chih-Hsiang Chang

En-Hui Zhang

Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019

Hardware Implementation for Multiple Activation Functions.

[BibT_eX]

[DOI]

Chih-Hsiang Chang

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

IC Camouflaging by Using Universal Gates under Timing Constraints.

[BibT_eX]

[DOI]

Po-Chieh Chang

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

3D Test Wrapper Chain Optimization with I/O Cells Binding Considered.

[BibT_eX]

[DOI]

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

TSV-aware 3D test wrapper chain optimization.

[BibT_eX]

[DOI]

Yu-Yi Wu

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Keynote Talk: 3D Core-based SoC Testing for Low Power and TSV Count Minimization.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on Network on Chip Architectures, 2018

An Effective Approach for Building Low-Power General Activity-Driven Clock Trees.

[BibT_eX]

[DOI]

Chen-Hsien Lin

Wei-Kai Cheng

Proceedings of the International SoC Design Conference, 2018

Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction.

[BibT_eX]

[DOI]

Wei-Kai Cheng

Jian-Kai Chen

Proceedings of the International SoC Design Conference, 2018

2017

Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Overview of the 2017 CAD contest at ICCAD: Invited paper.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints.

[BibT_eX]

[DOI]

Yen-Chun Ko

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Power-mode-aware buffer synthesis for low-power clock skew minimization.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

Top-level activity-driven clock tree synthesis with clock skew variation considered.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Overview of the 2016 CAD contest at ICCAD.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Clock Period Minimization with Minimum Leakage Power.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

Overview of the 2015 CAD Contest at ICCAD.

[BibT_eX]

[DOI]

Natarajan Viswanathan

Rung-Bin Lin

Myung-Chul Kim

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014

Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Leakage-power-aware clock period minimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Live demonstration: A low-power high-level synthesis system.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew.

[BibT_eX]

[DOI]

Tsung-Tang Lin

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Low-power anti-aging zero skew clock gating.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Low-power timing closure methodology for ultra-low voltage designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Co-synthesis of data paths and clock control paths for minimum-period clock gating.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

High-Level Synthesis for Minimum-Area Low-Power Clock Gating.

[BibT_eX]

[DOI]

Bing-Hung Li

J. Inf. Sci. Eng., 2012

A formal approach to slack-driven high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

NBTI-aware dual threshold voltage assignment for leakage power reduction.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Simultaneous wafer bonding type selection and layer assignment for TSV count minimization.

[BibT_eX]

[DOI]

Wei-Shuo Tzeng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Accurate TSV Number Minimization in High-Level Synthesis.

[BibT_eX]

[DOI]

Chih-Hung Lee

J. Inf. Sci. Eng., 2011

Minimum Inserted Buffers for Clock Period Minimization.

[BibT_eX]

[DOI]

Guan-Yu Jhuo

Wei-Lun Huang

J. Inf. Sci. Eng., 2011

TSV sharing through multiplexing for TSV count minimization in high-level synthesis.

[BibT_eX]

[DOI]

Yen-Hsin Lee

Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

Teaching three-dimensional system-in-package design automation in a semester course.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

2010

Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2010

Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Opposite-phase register switching for peak current minimization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Minimum-Period Register Binding.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization.

[BibT_eX]

[DOI]

Da-Chen Tzeng

J. Inf. Sci. Eng., 2009

Synthesis of Anti-Aging Gated Clock Designs.

[BibT_eX]

[DOI]

Song-Bin Pan

J. Inf. Sci. Eng., 2009

An ILP approach to surge current minimization in high-level synthesis.

[BibT_eX]

[DOI]

Jheng-Fu Yeh

IEICE Electron. Express, 2009

Surge Current Minimization in High-level Synthesis.

[BibT_eX]

[DOI]

Jheng-Fu Yeh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Timing driven power gating in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Power-Management Scheduling for Peak Power Minimization.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2008

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Module binding for low power clock gating.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2008

Type-matching clock tree for zero skew clock gating.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Clock skew scheduling with race conditions considered.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2007

Opposite-Phase Clock Tree for Peak Current Reduction.

[BibT_eX]

[DOI]

Sheng-Yu Hsu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Operation scheduling for the synthesis of false loop free circuits.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2007

Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential.

[BibT_eX]

[DOI]

Wei-Ting Yen

Proceedings of the Emerging Directions in Embedded and Ubiquitous Computing, 2007

A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs.

[BibT_eX]

[DOI]

Chu-Liao Wang

Man-Lin Huang

Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2007

Clock Period Minimization with Minimum Delay Insertion.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

2006

Synthesis of nonzero clock skew circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An ILP Approach to the Slack Driven Scheduling Problem.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

High-Speed Fuzzy Inference Processor Using Active Rules Identification.

[BibT_eX]

[DOI]

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management.

[BibT_eX]

[DOI]

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

State re-encoding for peak current minimization.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Fast multi-domain clock skew scheduling for peak current reduction.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Peak Power Minimization through Power Management Scheduling.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Operation Scheduling for False Loop Free Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2005

A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Three-dimension scheduling under multi-cycle interconnect communications.

[BibT_eX]

[DOI]

Chung-Hsin Chiang

IEICE Electron. Express, 2005

Floorplanning with clock tree estimation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

VLSI implementation of type-2 fuzzy inference processor.

[BibT_eX]

[DOI]

Yi-Rung Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A formal approach to the slack driven scheduling problem in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Minimizing peak current via opposite-phase clock tree.

[BibT_eX]

[DOI]

Sheng-Yu Hsu

Proceedings of the 42nd Design Automation Conference, 2005

Race-condition-aware clock skew scheduling.

[BibT_eX]

[DOI]

Feng-Pin Lu

Proceedings of the 42nd Design Automation Conference, 2005

2004

A Timing Driven Crosstalk Optimizer for Gridded Channel Routing.

[BibT_eX]

[DOI]

Yi-Siang Hsu

Chiu-Cheng Lin

IEICE Trans. Inf. Syst., 2004

2003

Clock Period Minimization of Non-Zero Clock Skew Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

An effective floorplan-based power distribution network design methodology under reliability constraints.

[BibT_eX]

[DOI]

Chu-Liao Wang

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions.

[BibT_eX]

[DOI]

Wen-Hon Peng

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

A timing driven approach for crosstalk minimization in gridded channel routing.

[BibT_eX]

[DOI]

Yi-Siang Hsu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

An effective low power design methodology based on interconnect prediction.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

A High Speed VLSI Fuzzy Logic Controller With Pipeline Architecture.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Conference on Fuzzy Systems, 2001

2000

A Reliable Clock Tree Design Methodology for ASIC Designs.

[BibT_eX]

[DOI]

Mely Chen Chi

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1995

A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits.

[BibT_eX]

[DOI]