Meng-Ting Tsai

According to our database, Meng-Ting Tsai authored at least 12 papers between 2005 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects.

Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Tsai, Wu-Tung Cheng

IEEE Des. Test, 2016

Versatile Transition-Time Monitoring for Interconnects via Distributed TDC.

Shi-Yu Huang, Chih-Chieh Cheng, Meng-Ting Tsai, Kuan-Chen Huang, Kun-Han Tsai, Wu-Tung Cheng

IEEE Des. Test, 2016

2015

General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects.

Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects.

Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Monitoring the delay of long interconnects via distributed TDC.

Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng

Proceedings of the 2015 IEEE International Test Conference, 2015

Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects.

Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013

Fault-Tolerant Control for Six-Phase PMSM Drive System via Intelligent Complementary Sliding-Mode Control Using TSKFNN-AMF.

Faa-Jeng Lin, Ying-Chih Hung, Meng-Ting Tsai

IEEE Trans. Ind. Electron., 2013

2007

A Fast-Locking Agile Frequency Synthesizer for MIMO Dual-mode WiFi / WiMAX Applications.

Meng-Ting Tsai, Ching-Yuan Yang

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

High-Frequency Low-Noise Voltage-Controlled <i>LC</i>-Tank Oscillators Using a Tunable Inductor Technique.

Ching-Yuan Yang, Meng-Ting Tsai

IEICE Trans. Electron., 2006

A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique.

Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels.

Meng-Ting Tsai, Ching-Yuan Yang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A high-frequency phase-compensation fractional-N frequency synthesizer.

Ching-Yuan Yang, Jen-Wen Chen, Meng-Ting Tsai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005