Michael D. Ciletti

According to our database1, Michael D. Ciletti authored at least 11 papers between 1969 and 1995.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Bibliography

1995
ADM: A New Technique for the Simulation of CMOS Circuit Transients.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Reducing correlation to improve coverage of delay faults in scan-path design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1992
Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

A quantitative measure of robustness for delay fault testing.
Proceedings of the conference on European design automation, 1992

1991
Correlation-Reduced Scan-path Design To Improve Delay Fault Coverage.
Proceedings of the 28th Design Automation Conference, 1991

1990
DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Arrangement of latches in scan-path design to improve delay fault coverage.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage Faults.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

A Variable Observation Time Method for Testing Delay Faults.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
A Simplified Six-waveform Type Method for Delay Fault Testing.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1969
Applications of optimal control theory to computer controller design: William S. Widnall: M.I.T. Press, Cambridge, Mass. Research monograph no. 48. (1968), 210 pp.
Autom., 1969


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