Michael D. Powell

According to our database1, Michael D. Powell authored at least 16 papers between 2001 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2011
Achieving uniform performance and maximizing throughput in the presence of heterogeneity.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2009
Architectural core salvaging in a multi-core processor for hard-error tolerance.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

CAMP: A technique to estimate per-structure power at run-time using a few simple parameters.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2007
Resource area dilation to reduce power density in throughput servers.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

2005
Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

Optimizing Replication, Communication, and Capacity Allocation in CMPs.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004
Exploiting Resonant Behavior to Reduce Inductive Noise.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Heat-and-run: leveraging SMT and CMP to manage power density through the operating system.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2003
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures.
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003

Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002
Reducing register ports for higher speed and lower energy.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2001
Reducing leakage in a high-performance deep-submicron instruction cache.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Reducing set-associative cache energy via way-prediction and selective direct-mapping.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001


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