Kaushik Roy
Orcid: 0000000207359695Affiliations:
 Purdue University, West Lafayette, IN, USA
According to our database^{1},
Kaushik Roy
authored at least 874 papers
between 1988 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Artif. Intell., June, 2024
Encoding Hierarchical Information in Neural Networks Helps in Subpopulation Shift.
IEEE Trans. Artif. Intell., February, 2024
Hardware/Software CoDesign With ADCLess InMemory Computing Hardware for Spiking Neural Networks.
IEEE Trans. Emerg. Top. Comput., 2024
EVPlanner: EnergyEfficient Robot Navigation via EventBased PhysicsGuided Neuromorphic Planner.
IEEE Robotics Autom. Lett., 2024
SWANN: Shuffling Weights in Crossbar Arrays for Enhanced DNN Accuracy in Deeply Scaled Technologies.
CoRR, 2024
LLS: Local Learning Rule for Deep Neural Networks Inspired by Neural Activity Synchronization.
CoRR, 2024
CoRR, 2024
CoRR, 2024
AdaGossip: Adaptive Consensus Stepsize for Decentralized Deep Learning with Communication Compression.
CoRR, 2024
CoRR, 2024
CoRR, 2024
EvEdge: Efficient Execution of Eventbased Vision Algorithms on Commodity Edge Platforms.
CoRR, 2024
HCiM: ADCLess Hybrid AnalogDigital Compute in Memory Accelerator for Deep Learning Workloads.
CoRR, 2024
Pruning for Improved ADC Efficiency in Crossbarbased Analog Inmemory Accelerators.
CoRR, 2024
Verifix: PostTraining Correction to Improve Label Noise Robustness with Verified Samples.
CoRR, 2024
CoRR, 2024
CoRR, 2024
PromptBased Bias Calibration for Better Zero/FewShot Learning of Language Models.
CoRR, 2024
CoRR, 2024
CoRR, 2024
TOFU: Toward Obfuscated Federated Updates by Encoding Weight Updates Into Gradients From Proxy Data.
IEEE Access, 2024
IEEE Access, 2024
HALSIE: Hybrid Approach to Learning Segmentation by Simultaneously Exploiting Image and Event Modalities.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
Crossfeature Contrastive Loss for Decentralized Deep Learning on Heterogeneous Data.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms to Hardware.
ACM Comput. Surv., December, 2023
IEEE Trans. Computers, September, 2023
IEEE Trans. Very Large Scale Integr. Syst., August, 2023
Online continual learning with saliencyguided experience replay using tiny episodic memory.
Mach. Vis. Appl., July, 2023
DIETSNN: A LowLatency Spiking Neural Network With Direct Input Encoding and Leakage and Threshold Optimization.
IEEE Trans. Neural Networks Learn. Syst., June, 2023
IEEE Trans. Artif. Intell., June, 2023
CoRR, 2023
Deep Unlearning: Fast and Efficient Trainingfree Approach to Controlled Forgetting.
CoRR, 2023
CoRR, 2023
CoRR, 2023
Best of Both Worlds: Hybrid SNNANN Architecture for Eventbased Optical Flow Estimation.
CoRR, 2023
CoRR, 2023
Homogenizing NonIID datasets via InDistribution Knowledge Distillation for Decentralized Learning.
CoRR, 2023
CoRR, 2023
CoRR, 2023
IEEE Access, 2023
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2023
Global Update Tracking: A Decentralized Learning Algorithm for Heterogeneous Data.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
RAMPNet: A Robust Adaptive MPC for Quadrotors via Physicsinformed Neural Network.
Proceedings of the IEEE International Conference on Robotics and Automation, 2023
DOTIE  Detecting Objects through Temporal Isolation of Events using a Spiking Architecture.
Proceedings of the IEEE International Conference on Robotics and Automation, 2023
AdaptiveSpikeNet: Eventbased Optical Flow Estimation using Spiking Neural Networks with Learnable Neuronal Dynamics.
Proceedings of the IEEE International Conference on Robotics and Automation, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
Proceedings of the Gaze Meets Machine Learning Workshop, 2023
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2023, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Live Demonstration: Realtime Eventbased Speed Detection using Spiking Neural Networks.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
Live Demonstration: ANN vs SNN vs Hybrid Architectures for Eventbased Realtime Gesture Recognition and Optical Flow Estimation.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023
A 65 nm 1.46.7 TOPS/W AdaptiveSNR SparsityAware CIM Core with Load Balancing Support for DL workloads.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
Proceedings of the 34th British Machine Vision Conference 2023, 2023
Proceedings of the ThirtySeventh AAAI Conference on Artificial Intelligence, 2023
2022
On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
NeuroIsing: Accelerating LargeScale Traveling Salesman Problems via Graph Neural Network Guided Localized Ising Solvers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Neural Networks, 2022
Eventbased Temporally Dense Optical Flow Estimation with Sequential Neural Networks.
CoRR, 2022
Neighborhood Gradient Clustering: An Efficient Decentralized Learning Method for NonIID Data Distributions.
CoRR, 2022
A Codesign view of Compute inMemory with NonVolatile Elements for Neural Networks.
CoRR, 2022
CoRR, 2022
CoRR, 2022
TOFU: Towards Obfuscated Federated Updates by Encoding Weight Updates into Gradients from Proxy Data.
CoRR, 2022
Adv. Intell. Syst., 2022
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
FusionFlowNet: EnergyEfficient Optical Flow Estimation using Sensor Fusion and Deep Fused SpikingAnalog Network Architectures.
Proceedings of the 2022 International Conference on Robotics and Automation, 2022
RAPIDRL: A Reconfigurable Architecture with PreemptiveExits for Efficient DeepReinforcement Learning.
Proceedings of the 2022 International Conference on Robotics and Automation, 2022
Design Space and Memory Technology CoExploration for InMemory Computing Based Machine Learning Accelerators.
Proceedings of the 41st IEEE/ACM International Conference on ComputerAided Design, 2022
InMemory Computing based Machine Learning Accelerators: Opportunities and Challenges.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Towards Ultra Low Latency Spiking Neural Networks for Vision and Sequential Tasks Using Temporal Pruning.
Proceedings of the Computer Vision  ECCV 2022, 2022
Towards ADCLess ComputeInMemory Accelerators for Energy Efficient Deep Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
HyperX: A Hybrid RRAMSRAM partitioned system for error recovery in memristive Xbars.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Spiking Neural Networks with Improved Inherent Recurrence Dynamics for Sequential Learning.
Proceedings of the ThirtySixth AAAI Conference on Artificial Intelligence, 2022
Oscillatory Fourier Neural Network: A Compact and Efficient Architecture for Sequential Processing.
Proceedings of the ThirtySixth AAAI Conference on Artificial Intelligence, 2022
Approximate Computing for Machine Learning Workloads: A Circuits and Systems Perspective.
Proceedings of the Approximate Computing, 2022
2021
STDP Based Unsupervised Multimodal Learning With CrossModal Processing in Spiking Neural Networks.
IEEE Trans. Emerg. Top. Comput. Intell., 2021
Magnetoresistive Circuits and Systems: Embedded NonVolatile Memory to Crossbar Arrays.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Neural Networks, 2021
Neurocomputing, 2021
Editorial: Understanding and Bridging the Gap Between Neuromorphic Computing and Machine Learning.
Frontiers Comput. Neurosci., 2021
Quantifying the Brain Predictivity of Artificial Neural Networks With Nonlinear Response Mapping.
Frontiers Comput. Neurosci., 2021
IEEE Des. Test, 2021
CoRR, 2021
CoRR, 2021
CoRR, 2021
One Timestep is All You Need: Training Spiking Neural Networks with Ultra Low Latency.
CoRR, 2021
NAX: CoDesigning Neural Network and Hardware Architecture for Memristive Xbar based Computing Systems.
CoRR, 2021
IMPULSE: A 65nm Digital ComputeinMemory Macro with Fused Weights and Membrane Potential for Spikebased Sequential Learning Tasks.
CoRR, 2021
Network Compression via Mixed Precision Quantization Using a MultiLayer Perceptron for the BitWidth Allocation.
IEEE Access, 2021
SPACE: Structured Compression and Sharing of Representational Space for Continual Learning.
IEEE Access, 2021
Enabling Robust SOTMTJ Crossbars for Machine Learning using SparsityAware DeviceCircuit Codesign.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
SelfSupervised Optical Flow with Spiking Neural Networks and Event Based Cameras.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021
Proceedings of the International Joint Conference on Neural Networks, 2021
Accurate and Accelerated Neuromorphic Network Design Leveraging A Bayesian Hyperparameter Pareto Optimization Approach.
Proceedings of the ICONS 2021: International Conference on Neuromorphic Systems 2021, 2021
Proceedings of the 9th International Conference on Learning Representations, 2021
Complexityaware Adaptive Training and Inference for EdgeCloud Distributed AI Systems.
Proceedings of the 41st IEEE International Conference on Distributed Computing Systems, 2021
DCTSNN: Using DCT to Distribute Spatial Information over Time for LowLatency Spiking Neural Networks.
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021
BrainInspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Exploring SpikeBased Learning for Neuromorphic Computing: Prospects and Perspectives.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Hybrid AnalogSpiking Long ShortTerm Memory for Energy Efficient Computing on Edge Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
sBSNN: StochasticBits Enabled Binary Spiking Neural Network With OnChip Learning for Energy Efficient Neuromorphic Computing at the Edge.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst., 2020
Functional Read Enabling InMemory Computations in 1Transistor  1Resistor Memory Arrays.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
TraNNsformer: Clustered Pruning on CrossbarBased Architectures for EnergyEfficient Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
PANTHER: A Programmable Architecture for Neural Network Training Harnessing EnergyEfficient ReRAM.
IEEE Trans. Computers, 2020
Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges.
Proc. IEEE, 2020
TreeCNN: A hierarchical Deep Convolutional Neural Network for incremental learning.
Neural Networks, 2020
Constructing energyefficient mixedprecision neural networks through principal component analysis for edge intelligence.
Nat. Mach. Intell., 2020
Circuits and Architectures for InMemory ComputingBased Machine Learning Accelerators.
IEEE Micro, 2020
Erratum to "CASHRAM: Enabling InMemory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8TSRAM Arrays".
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
CASHRAM: Enabling InMemory Computations for Edge Inference Using Charge Accumulation and Sharing in Standard 8TSRAM Arrays.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2020
Exploring Vicinal Risk Minimization for Lightweight OutofDistribution Detection.
CoRR, 2020
DCTSNN: Using DCT to Distribute Spatial Information over Time for Learning LowLatency Spiking Neural Networks.
CoRR, 2020
Robustness Hidden in Plain Sight: Can Analog Computing Defend Against Adversarial Attacks?
CoRR, 2020
DIETSNN: Direct Input Encoding With Leakage and Threshold Optimization in Deep Spiking Neural Networks.
CoRR, 2020
CoRR, 2020
CoRR, 2020
RMPSNNs: Residual Membrane Potential Neuron for Enabling Deeper HighAccuracy and LowLatency Spiking Neural Networks.
CoRR, 2020
Explicitly Trained Spiking Sparsity in Spiking Neural Networks with Backpropagation.
CoRR, 2020
Relevantfeatures based Auxiliary Cells for Energy Efficient Detection of Natural Errors.
CoRR, 2020
Structured Compression and Sharing of Representational Space for Continual Learning.
CoRR, 2020
Incremental Learning in Deep Convolutional Neural Networks Using Partial Network Sharing.
IEEE Access, 2020
IEEE Access, 2020
Gradual Channel Pruning While Training Using Feature Relevance Scores for Convolutional Neural Networks.
IEEE Access, 2020
Invited Talk: ReEngineering Computing with NeuroInspired Learning: Devices, Circuits, and Systems.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
EnergyEfficient Target Recognition using ReRAM Crossbars for Enabling OnDevice Intelligence.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
InsulatorMetal Transition Material Based Artificial Neurons: A Design Perspective.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
RAMANN: inSRAM differentiable memory computations for memoryaugmented neural networks.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Hyperparameter Optimization in Binary Communication Networks for Neuromorphic Deployment.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Enabling Homeostasis using Temporal Decay Mechanisms in Spiking CNNs Trained with Unsupervised Spike Timing Dependent Plasticity.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Enabling Deep Spiking Neural Networks with Hybrid Conversion and Spike Timing Dependent Backpropagation.
Proceedings of the 8th International Conference on Learning Representations, 2020
Training Deep Spiking Neural Networks for EnergyEfficient Neuromorphic Computing.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020
Inherent Adversarial Robustness of Deep Spiking Neural Networks: Effects of Discrete Input Encoding and Nonlinear Activations.
Proceedings of the Computer Vision  ECCV 2020, 2020
SpikeFlowNet: EventBased Optical Flow Estimation with EnergyEfficient Hybrid Neural Networks.
Proceedings of the Computer Vision  ECCV 2020, 2020
Proceedings of the Computer Vision  ECCV 2020, 2020
GENIEx: A Generalized Approach to Emulating NonIdeality in Memristive Xbars using Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
InMemory Computing in Emerging Memory Technologies for Machine Learning: An Overview.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
RMPSNN: Residual Membrane Potential Neuron for Enabling Deeper HighAccuracy and LowLatency Spiking Neural Network.
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through MixedSignal Neurons.
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
XcelRAM: Accelerating Binary Neural Networks in HighThroughput SRAM Compute Arrays.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
STDPBased Pruning of Connections and Weight Quantization in Spiking Neural Networks for EnergyEfficient Recognition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
SPARE: Spiking Neural Network Acceleration Using ROMEmbedded RAMs as InMemoryComputation Primitives.
IEEE Trans. Computers, 2019
Deep Spiking Convolutional Neural Network Trained With Unsupervised SpikeTimingDependent Plasticity.
IEEE Trans. Cogn. Dev. Syst., 2019
Neural network accelerator design with resistive crossbars: Opportunities and challenges.
IBM J. Res. Dev., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Towards Scalable, Efficient and Accurate Deep Spiking Neural Networks with Backward Residual Connections, Stochastic Softmax and Hybridization.
CoRR, 2019
XCHANGR: Changing Memristive Crossbar Mapping for Mitigating LineResistance Induced Accuracy Degradation in Deep Neural Networks.
CoRR, 2019
Synthesizing Images from SpatioTemporal Representations using Spikebased Backpropagation.
CoRR, 2019
CoRR, 2019
CoRR, 2019
Enabling Spikebased Backpropagation in Stateoftheart Deep Neural Network Architectures.
CoRR, 2019
ReStoCNet: Residual Stochastic Binary Convolutional Spiking Neural Network for MemoryEfficient Neuromorphic Computing.
CoRR, 2019
Stimulating STDP to Exploit Locality for Lifelong Learning without Catastrophic Forgetting.
CoRR, 2019
Efficient Hybrid Network Architectures for Extremely Quantized Neural Networks Enabling Intelligence at the Edge.
CoRR, 2019
Discretization Based Solutions for Secure Machine Learning Against Adversarial Attacks.
IEEE Access, 2019
Proceedings of the IEEE International Conference on Smart Computing, 2019
Proceedings of the 16th IEEE International Conference on Mobile Ad Hoc and Sensor Systems, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
Evaluating the Stability of Recurrent Neural Models during Training with Eigenvalue Spectra Analysis.
Proceedings of the International Joint Conference on Neural Networks, 2019
On Robustness of SpinOrbitTorque Based Stochastic Sigmoid Neurons for Spiking Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2019
Proceedings of the 2019 IEEE International Conference on Cognitive Computing, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
PABO: Pseudo AgentBased MultiObjective Bayesian Hyperparameter Optimization for Efficient Neural Accelerator Design.
Proceedings of the International Conference on ComputerAided Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 IEEE International Conference on Big Data (IEEE BigData), 2019
PUMA: A Programmable Ultraefficient Memristorbased Accelerator for Machine Learning Inference.
Proceedings of the TwentyFourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Designing EnergyEfficient Intermittently Powered Systems Using SpinHallEffectBased Nonvolatile SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
DeltaFrameBP: An Algorithm Using Frame Difference for Deep Convolutional Neural Networks Training and Inference on Video Data.
IEEE Trans. Multi Scale Comput. Syst., 2018
CrossLayer Design Exploration for EnergyQuality Tradeoffs in Spiking and NonSpiking Deep Artificial Neural Networks.
IEEE Trans. Multi Scale Comput. Syst., 2018
An AllMemristor Deep Spiking Neural Computing System: A Step Toward Realizing the LowPower Stochastic Brain.
IEEE Trans. Emerg. Top. Comput. Intell., 2018
Technology Aware Training in Memristive Neuromorphic Systems for Nonideal Synaptic Crossbars.
IEEE Trans. Emerg. Top. Comput. Intell., 2018
XSRAM: Enabling InMemory Boolean Computations in CMOS Static Random Access Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Microelectron. Reliab., 2018
STDPbased Unsupervised Feature Learning using Convolutionovertime in Spiking Neural Networks for EnergyEfficient Neuromorphic Computing.
ACM J. Emerg. Technol. Comput. Syst., 2018
ACM J. Emerg. Technol. Comput. Syst., 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
ASP: Learning to Forget With Adaptive Synaptic Plasticity in Spiking Neural Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
RxCaffe: Framework for evaluating and training Deep Neural Networks on Resistive Crossbars.
CoRR, 2018
CoRR, 2018
Explainable Learning: Implicit Generative Modelling during Training for Adversarial Robustness.
CoRR, 2018
XcelRAM: Accelerating Binary Neural Networks in HighThroughput SRAM Compute Arrays.
CoRR, 2018
Exploiting Inherent ErrorResiliency of Neuromorphic Computing to achieve Extreme EnergyEfficiency through MixedSignal Neurons.
CoRR, 2018
AllPhotonic Phase Change Spiking Neuron: Toward Fast Neural Computing using Light.
CoRR, 2018
Proposal for a Low Voltage AnalogtoDigital Converter using Voltage Controlled Stochastic Switching of Low Barrier Nanomagnets.
CoRR, 2018
Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency.
CoRR, 2018
CoRR, 2018
CoRR, 2018
CoRR, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Analysis of Bridge Defects in STTMRAM Cells Under Process Variations and a Robust DFT Technique for Their Detection.
Proceedings of the VLSISoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
HardwareSoftware CoDesign for an AnalogDigital Accelerator for Machine Learning.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
FALCON: Feature Driven Selective Classification for EnergyEfficient Image Recognition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Investigation of dependence between timezero and timedependent variability in highκ NMOS transistors.
Microelectron. Reliab., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
Chaosguided Input Structuring for Improved Learning in Recurrent Neural Networks.
CoRR, 2017
XSRAM: Enabling InMemory Boolean Computations in CMOS Static Random Access Memories.
CoRR, 2017
An AllMemristor Deep Spiking Neural Network: A Step Towards Realizing the Low Power, Stochastic Brain.
CoRR, 2017
Technology Aware Training in Memristive Neuromorphic Systems based on nonideal Synaptic Crossbars.
CoRR, 2017
SPARE: Spiking Networks Acceleration Using CMOS ROMEmbedded RAM as an InMemoryComputation Primitive.
CoRR, 2017
Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing.
CoRR, 2017
Magnetic Tunnel Junction Enabled Stochastic Spiking Neural Networks: From NonTelegraphic to Telegraphic Switching Regime.
CoRR, 2017
CoRR, 2017
Convolutional Spike Timing Dependent Plasticity based Feature Learning in Spiking Neural Networks.
CoRR, 2017
CoRR, 2017
Proposal for a Leaky Integrate Fire Spiking Neuron Using Voltage Driven Domain Wall Motion.
CoRR, 2017
Proceedings of the 14th International Conference on Synthesis, 2017
Energy efficient computation using injection locked biasfield free spinhall nanooscillator array with shared heavy metal.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Gabor filter assisted energy efficient fast learning Convolutional Neural Networks.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Spintorque sensors with differential signaling for fast and energy efficient global interconnects.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Spike timing dependent plasticity based enhanced selflearning for efficient pattern recognition in spiking neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Performance analysis and benchmarking of allspin spiking neural networks (Special session paper).
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
EnsembleSNN: Distributed assistive STDP learning for energyefficient recognition in spiking neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Convolving over time via recurrent connections for sequential weight sharing in neural networks.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
An EnergyEfficient MixedSignal Neuron for Inherently ErrorResilient Neuromorphic Systems.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Stochastic Switching of SHEMTJ as a Natural Annealer for Efficient Combinatorial Optimization.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
TraNNsformer: Neural network transformation for memristive crossbar based neuromorphic system design.
Proceedings of the 2017 IEEE/ACM International Conference on ComputerAided Design, 2017
Staged Inference using Conditional Deep Learning for energy efficient realtime smart diagnosis.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Fast, low power evaluation of elementary functions using radial basis function networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
RESPARC: A Reconfigurable and EnergyEfficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
LowPower System for Detection of Symptomatic Patterns in Audio Biological Signals.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Hierarchical Temporal Memory Based on SpinNeurons and Resistive Memory for EnergyEfficient BrainInspired Computing.
IEEE Trans. Neural Networks Learn. Syst., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Computers, 2016
Proposal for an AllSpin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in Ferromagnets.
IEEE Trans. Biomed. Circuits Syst., 2016
Proc. IEEE, 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
Asymmetric Underlapped FinFETs for Near and SuperThreshold Logic at Sub10nm Technology Nodes.
ACM J. Emerg. Technol. Comput. Syst., 2016
High Performance and EnergyEfficient OnChip Cache Using Dual Port (1R/1W) SpinOrbit Torque MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on InPlane and Perpendicular Anisotropies.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Integrated Systems in the MoreThanMoore Era: Designing LowCost EnergyEfficient Systems Using Heterogeneous Components.
IEEE Des. Test, 2016
Ising spin model using SpinHall Effect (SHE) induced magnetization reversal in MagneticTunnelJunction.
CoRR, 2016
CoRR, 2016
Attention Tree: Learning Hierarchies of Visual Features for LargeScale Image Recognition.
CoRR, 2016
Proposal for a LeakyIntegrateFire Spiking Neuron based on MagnetoElectric Switching of Ferromagnets.
CoRR, 2016
CoRR, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the 17th LatinAmerican Test Symposium, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Spintronic devices for ultralow power neuromorphic computation (Special session paper).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A lowvoltage, low power STDP synapse implementation using domainwall magnets for spiking neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Unsupervised regenerative learning of hierarchical features in Spiking Deep Networks for object recognition.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Unsupervised incremental STDP learning using forced firing of dormant or idle neurons.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Design of powerefficient approximate multipliers for approximate artificial neural networks.
Proceedings of the 35th International Conference on ComputerAided Design, 2016
Significance driven hybrid 8T6T SRAM for energyefficient synaptic storage in artificial neural networks.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Multiplierless Artificial Neurons exploiting error resiliency for energyefficient neural computing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Lowpower approximate convolution computing unit with domainwall motion based "spinmemristor" for image processing applications.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Invited  Crosslayer approximations for neuromorphic computing: from devices to circuits and systems.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Prospects of efficient neural computing with arrays of magnetometallic neurons and synapses.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Highly Reliable SpinTransfer Torque Magnetic RAMBased Physical Unclonable Function With MultiResponseBits Per Cell.
IEEE Trans. Inf. Forensics Secur., 2015
Optimizating Emerging Nonvolatile Memories for DualMode Applications: Data Storage and Key Generator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Microelectron. Reliab., 2015
EnergyEfficient AllSpin Cache Hierarchy Using ShiftBased Writes and Multilevel Storage.
ACM J. Emerg. Technol. Comput. Syst., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
CoRR, 2015
Simulation studies of an AllSpin Artificial Neural Network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets.
CoRR, 2015
ShortTerm Plasticity and LongTerm Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses.
CoRR, 2015
CoRR, 2015
Hybrid SpintronicCMOS Spiking Neural Network With OnChip Learning: Devices, Circuits and Systems.
CoRR, 2015
Object Detection using Semantic Decomposition for EnergyEfficient Neural Computing.
CoRR, 2015
Energy Efficient and High Performance CurrentMode Neural Network Circuit using Memristors and Digitally Assisted Analog CMOS Neurons.
CoRR, 2015
CoRR, 2015
Approximate Computing: An EnergyEfficient Computing Technique for Error Resilient Applications.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Domain wall motionbased low power hybrid spinCMOS 5bit Flash Analog Data Converter.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
Spintastic: <u>spin</u>based s<u>t</u>och<u>astic</u> logic for energyefficient computing.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
DyReCTape: a <u>dy</u>namically <u>re</u>configurable <u>c</u>ache using domain wall memory <u>tape</u>s.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STTMRAM Cache Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
DataDependent Operation SpeedUp Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Microelectron. J., 2014
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
CoRR, 2014
CoRR, 2014
STTSNN: A SpinTransferTorque Based SoftLimiting NonLinear Neuron for LowPower Artificial Neural Networks.
CoRR, 2014
CoRR, 2014
CoRR, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Highly reliable memorybased Physical Unclonable Function using SpinTransfer Torque MRAM.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Workload dependent evaluation of thinfilm thermoelectric devices for onchip cooling and energy harvesting.
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 2014
Proceedings of the 12th IEEE Symposium on Embedded Systems for Realtime Multimedia, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
"All Programmable SOC FPGA for networking and computing in big data infrastructure".
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Computers, 2013
ACM J. Emerg. Technol. Comput. Syst., 2013
IEEE Des. Test, 2013
Spintronic Switches for Ultra Low Energy OnChip and InterChip CurrentMode Interconnects
CoRR, 2013
CoRR, 2013
CoRR, 2013
CoRR, 2013
CoRR, 2013
Energy efficient computing using coupled DualPillar Spin Torque Nano Oscillators.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
Design of ultra high density and low power computational blocks using nanomagnets.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Multilevel magnetic RAM using domain wall shift for energyefficient, highdensity caches.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Beyond chargebased computation: Boolean and nonBoolean computing with spin torque devices.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 2013 IEEE 19th International OnLine Testing Symposium (IOLTS), 2013
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
DWMTAPESTRI  an energy efficient allspin cache using domain wall shift based writes.
Proceedings of the Design, Automation and Test in Europe, 2013
Substituteandsimplify: a unified design paradigm for approximate and quality configurable circuits.
Proceedings of the Design, Automation and Test in Europe, 2013
Ultra low power associative computing with spin neurons and resistive crossbar memory.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Analysis and characterization of inherent application resilience for approximate computing.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
Logic and Memory Design Based on Unequal Error Protection for Voltagescalable, Robust and Adaptive DSP Systems.
J. Signal Process. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
LowPower Architecture for Epileptic Seizure Detection Based on Reduced Complexity DWT.
ACM J. Emerg. Technol. Comput. Syst., 2012
J. Circuits Syst. Comput., 2012
Dagstuhl Reports, 2012
CoRR, 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
LowOverhead Maximum Power Point Tracking for MicroScale Solar Energy Harvesting Systems.
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Modeling, design and crosslayer optimization of polysilicon solar cell based microscale energy harvesting systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
A lowpower "nearthreshold" epileptic seizure detection processor with multiple algorithm programmability.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Spin based neuronsynapse module for ultra low power programmable computational networks.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Proceedings of the IEEE International Conference on IC Design & Technology, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Novel Low Overhead PostSilicon SelfCorrection Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Robust Level Converter for SubThreshold/SuperThreshold Operation: 100 mV to 2.5 V.
IEEE Trans. Very Large Scale Integr. Syst., 2011
A PriorityBased 6T/8T Hybrid SRAM Architecture for Aggressive Voltage Scaling in Video Applications.
IEEE Trans. Circuits Syst. Video Technol., 2011
Guest Editorial Advances in Design of EnergyEfficient Circuits and Systems (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Containing the Nanometer "PandoraBox": CrossLayer Design Techniques for Variation Aware Low Power Systems.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Energy efficient manycore processor for recognition and mining using spinbased memory.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Lowpower functionality enhanced computation architecture using spinbased devices.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Columnselectionenabled 8T SRAM array with ~1R/1W multiport operation for DVFSenabled processors.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on ComputerAided Design, 2011
Voltage overscaling: A crosslayer design perspective for energy efficient systems.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Stage number optimization for switched capacitor power converters in microscale energy harvesting.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 48th Design Automation Conference, 2011
Integrated Design & Test: Conquering the Conflicting Requirements of LowPower, VariationTolerance and Test Cost.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Variationtolerant and selfrepair design methodology for low temperature polycrystalline silicon liquid crystal and organic light emitting diode displays.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the LowPower VariationTolerant Design in Nanometer Silicon, 2011
2010
Energyefficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering.
J. Signal Process. Syst., 2010
Dynamic BitWidth Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Trifecta: A Nonspeculative Scheme to Exploit Common, DataDependent Subcritical Paths.
IEEE Trans. Very Large Scale Integr. Syst., 2010
A Scalable CircuitArchitecture CoDesign to Improve Memory Yield for HighPerformance Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Design Paradigm for Robust SpinTorque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.
IEEE Trans. Very Large Scale Integr. Syst., 2010
ProcessVariation Resilient and VoltageScalable DCT Architecture for Robust LowPower Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2010
OnChip Variability Sensor Using PhaseLocked Loop for Detecting and Correcting Parametric Timing Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2010
ABRM: Adaptive Beta Ratio Modulation for ProcessTolerant Ultradynamic Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Voltage Scalable HighSpeed Robust Hybrid Arithmetic Units Using Adaptive Clocking.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Characterization of Random Process Variations Using UltralowPower, HighSensitivity, BiasFree SubThreshold Process Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Digital Computation in Subthreshold Region for UltralowPower Operation: A DeviceCircuitArchitecture Codesign Perspective.
Proc. IEEE, 2010
Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era.
Proc. IEEE, 2010
Exploring Asynchronous Design Techniques for ProcessTolerant and EnergyEfficient Subthreshold Operation.
IEEE J. Solid State Circuits, 2010
Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling.
IET Circuits Devices Syst., 2010
Integrated Systems in the MorethanMoore Era: Designing LowCost EnergyEfficient Systems Using Heterogeneous Components.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Accurate characterization of random process variations using a robust lowvoltage highsensitivity sensor featuring replicabias circuit.
Proceedings of the IEEE International SolidState Circuits Conference, 2010
Lowpower DWTbased quasiaveraging algorithm and architecture for epileptic seizure detection.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
HERQULES: system level crosslayer design exploration for efficient energyquality tradeoffs.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010
Maximum power point considerations in microscale solar energy harvesting systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A selfconsistent model to estimate NBTI degradation and a comprehensive online system lifetime enhancement technique.
Proceedings of the 16th IEEE International OnLine Testing Symposium (IOLTS 2010), 2010
Proceedings of the 28th International Conference on Computer Design, 2010
MultipleParameter SideChannel Analysis: A Noninvasive Hardware Trojan Detection Approach.
Proceedings of the HOST 2010, 2010
Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis.
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Gated Decap: Gate Leakage Control of OnChip Decoupling Capacitors in Scaled Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Slope Interconnect Effort: GateInterconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for LowPower LowCost Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Design Methodology for Low Power and Parametric Robustness Through OutputQuality Modulation: Application to ColorInterpolation Filtering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
A 32 kb 10T SubThreshold SRAM Array With BitInterleaving and Differential Read Scheme in 90 nm CMOS.
IEEE J. Solid State Circuits, 2009
IEEE Des. Test Comput., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuning.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Significance driven computation: a voltagescalable, variationaware, qualitytuning motion estimator.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 46th Design Automation Conference, 2009
A voltagescalable & process variation resilient hybrid SRAM architecture for MPEG4 video processors.
Proceedings of the 46th Design Automation Conference, 2009
REad/accesspreferred (REAP) SRAM  architectureaware bit cell design for improved yield and lower VMIN.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Design for burnin test: a technique for burnin thermal stability under dietodie parameter variations.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
An alternate design paradigm for robust spintorque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
A design methodology and device/circuit/architecture compatible simulation framework for lowpower magnetic quantum cellular automata systems.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption.
J. Signal Process. Syst., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
WithinDie VariationAware Scheduling in Superscalar Processors for Improved Throughput.
IEEE Trans. Computers, 2008
An OnChip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
An alternate design paradigm for lowpower, lowcost, testable hybrid systems using scaled LTPS TFTs.
ACM J. Emerg. Technol. Comput. Syst., 2008
J. Electron. Test., 2008
Design and Analysis of a SelfRepairing SRAM with OnChip Monitor and Compensation Circuitry.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008
A 32kb 10T Subthreshold SRAM Array with BitInterleaving and Differential Read Scheme in 90nm CMOS.
Proceedings of the 2008 IEEE International SolidState Circuits Conference, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
O<sup>2</sup>C: occasional twocycle operations for dynamic thermal management in high performance inorder microprocessors.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
FaultTolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems.
Proceedings of the 23rd IEEE International Symposium on Defect and FaultTolerance in VLSI Systems (DFT 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Modeling of failure probability and statistical design of spintorque transfer magnetic random access memory (STT MRAM) array for yield enhancement.
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Exploring highspeed lowpower hybrid arithmetic units at scaled supply and adaptive clockstretching.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
DeviceAware YieldCentric DualV<sub>t</sub> Design Under Parameter Variations in Nanoscale Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Signal Process., 2007
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Carbon Nanotube Electronics: Design of HighPerformance and LowPower Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Impact of NegativeBias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
CRISTA: A New Paradigm for LowPower, VariationTolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
SelfConsistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Estimation of gatetochannel tunneling current in ultrathin oxide sub50nm double gate devices.
Microelectron. J., 2007
Design of a Process Variation Tolerant SelfRepairing SRAM for Yield Enhancement in Nanoscaled CMOS.
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing.
J. Low Power Electron., 2007
IEICE Trans. Electron., 2007
An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A generic and reconfigurable test paradigm using Lowcost integrated PolySi TFTs.
Proceedings of the 2007 IEEE International Test Conference, 2007
Characterization of NBTI induced temporal performance degradation in nanoscale SRAM array using IDDQ.
Proceedings of the 2007 IEEE International Test Conference, 2007
Power dissipation, variations and nanoscale CMOS design: Test challenges and selfcalibration/selfrepair solutions.
Proceedings of the 2007 IEEE International Test Conference, 2007
Statistical Characterization and OnChip Measurement Methods for Local Random Variability of a Process Using SenseAmplifierBased Test Structure.
Proceedings of the 2007 IEEE International SolidState Circuits Conference, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Lowpower processvariation tolerant arithmetic units using inputbased elastic clocking.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Slope interconnect effort: gateinterconnect interdependentdelay model for CMOS logic gates.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
A process variation aware low power synthesis methodology for fixedpoint FIR filters.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the 13th IEEE International OnLine Testing Symposium (IOLTS 2007), 2007
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering.
Proceedings of the 2007 International Conference on ComputerAided Design, 2007
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance.
Proceedings of the 2007 International Conference on ComputerAided Design, 2007
Proceedings of the 2007 International Conference on ComputerAided Design, 2007
An Optimal Algorithm for Low Power Multiplierless FIR Filter Design using Chebychev Criterion.
Proceedings of the IEEE International Conference on Acoustics, 2007
A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS.
Proceedings of the 33rd European SolidState Circuits Conference, 2007
Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Interactive presentation: Process tolerant betaratio modulation for ultradynamic voltage scaling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Lowoverhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 44th Design Automation Conference, 2007
Variation Resilient LowPower Circuit Design Methodology using OnChip Phase Locked Loop.
Proceedings of the 44th Design Automation Conference, 2007
Characterization and Estimation of Circuit Reliability Degradation under NBTI using OnLine IDDQ Measurement.
Proceedings of the 44th Design Automation Conference, 2007
FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
A novel highperformance and robust sense amplifier using independent gate control in sub50nm doublegate MOSFET.
IEEE Trans. Very Large Scale Integr. Syst., 2006
A process variation compensating technique with an ondie leakage current sensor for nanometer scale dynamic circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2006
A LeakageTolerant LowSwing Circuit Style in Partially Depleted SilicononInsulator CMOS Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.
ACM Trans. Design Autom. Electr. Syst., 2006
Modeling of metallic carbonnanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Modeling and analysis of loading effect on leakage of nanoscaled bulkCMOS logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Micro, 2006
IEEE J. Solid State Circuits, 2006
Integr., 2006
Integr., 2006
J. Electron. Test., 2006
IEEE Des. Test Comput., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Process Variation: Its Impact on the Design and Test of CMOS Circuits.
Proceedings of the 7th Latin American Test Workshop, 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 12th IEEE International OnLine Testing Symposium (IOLTS 2006), 2006
Efficient TransistorLevel Sizing Technique under Temporal Performance Degradation due to NBTI.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
A new paradigm for lowpower, variationtolerant circuit synthesis using critical path isolation.
Proceedings of the 2006 International Conference on ComputerAided Design, 2006
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.
Proceedings of the 2006 International Conference on ComputerAided Design, 2006
Ultralow power computing with subthreshold leakage: a comparative study of bulk and SOI technologies.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Dynamic bitwidth adaptation in DCT: image quality versus computation energy tradeoff.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Circuitaware device design methodology for nanometer technologies: a case study for low power SRAM design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Selfcalibration technique for reduction of hold failures in lowpower nanoscaled SRAM.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
A fully physical model for leakage distribution under process variations in Nanoscale doublegate CMOS.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Optimization of Surface Orientation for HighPerformance, LowPower and Robust FinFET SRAM.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
SAVS: a selfadaptive variable supplyvoltage technique for process tolerant and powerefficient multiissue superscalar processor design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASPDAC 2006, 2006
Lowoverhead design of softerrortolerant scan flipflops with enhancedscan capability.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASPDAC 2006, 2006
Speed binning aware design methodology to improve profit under parameter variations.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASPDAC 2006, 2006
Compact thermal models for estimation of temperaturedependent power/performance in FinFET technology.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASPDAC 2006, 2006
2005
Computing with subthreshold leakage: device/circuit/architecture codesign for ultralowpower subthreshold operation.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Combined circuit and architectural level variable supplyvoltage scaling for low power.
IEEE Trans. Very Large Scale Integr. Syst., 2005
A forward bodybiased lowleakage SRAM cache: device, circuit and architecture considerations.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Current demand balancing: a technique for minimization of current surge in high performance clockgated microprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
IEEE Trans. Very Large Scale Integr. Syst., 2005
A novel wavelet transformbased transient current analysis for fault detection and localization.
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
A processtolerant cache architecture for improved yield in nanoscale technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2005
ACM Trans. Design Autom. Electr. Syst., 2005
Synthesis of applicationspecific highly efficient multimode cores for embedded systems.
ACM Trans. Embed. Comput. Syst., 2005
CSDC: a new complexity reduction technique for multiplierless implementation of digital FIR filters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Accurate estimation of total leakage in nanometerscale bulk CMOS circuits based on device geometry and doping profile.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Trans. Computers, 2005
Estimation of delay variations due to randomdopant fluctuations in nanoscale CMOS circuits.
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
Process variation in embedded memories: failure analysis and variation aware architecture.
IEEE J. Solid State Circuits, 2005
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
J. Electron. Test., 2005
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.
J. Electron. Test., 2005
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Reliable and selfrepairing SRAM in nanoscale technologies using leakage and delay monitoring.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Design of High Performance Sense Amplifier Using Independent Gate Control in sub50nm DoubleGate MOSFET.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Modeling and Analysis of Gate Leakage in Ultrathin Oxide Sub50nm Double Gate Devices and Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Power Reduction in TestPerScan BIST with Supply Gating and Efficient Scan Partitioning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
An 8.3GHz dual supply/threshold optimized 32b integer ALUregister file loop in 90nm CMOS.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Cascaded carryselect adder (C<sup>2</sup>SA): a new structure for lowpower CSA design.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Effectiveness of low power dualV<sub>t</sub> designs in nanoscale technologies under process parameter variations.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
A new reducedcomplexity sphere decoder with true latticeboundaryawareness for multiantenna systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A novel lowcomplexity method for parallel multiplierless implementation of digital FIR filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Asymmetric halo CMOSFET to reduce static power dissipation with improved performance.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 11th IEEE International OnLine Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International OnLine Testing Symposium (IOLTS 2005), 2005
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub100nm Technology.
Proceedings of the 11th IEEE International OnLine Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International OnLine Testing Symposium (IOLTS 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 2005 International Conference on ComputerAided Design, 2005
Accurate estimation and modeling of total chip leakage considering inter & intradie process variations.
Proceedings of the 2005 International Conference on ComputerAided Design, 2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
A novel delay fault testing methodology using onchip lowoverhead delay measurement hardware at strategic probe points.
Proceedings of the 10th European Test Symposium, 2005
Modeling and Analysis of Loading Effect in Leakage of NanoScaled BulkCMOS Logic Circuits.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub100nm Technologies.
Proceedings of the 2005 Design, 2005
A Novel Lowoverhead Delay Testing Technique for Arbitrary TwoPattern Test Application.
Proceedings of the 2005 Design, 2005
A novel synthesis approach for active leakage power reduction using dynamic supply gating.
Proceedings of the 42nd Design Automation Conference, 2005
Fast and accurate estimation of nanoscaled SRAM read failure probability using critical point sampling.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Leakage Current Based Stabilization Scheme for Robust SenseAmplifier Design for Yield Enhancement in Nanoscale SRAM.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
A Statistical Approach to AreaConstrained Yield Enhancement for Pipelined Circuits under Parameter Variations.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Complexity reduction of digital filters using shift inclusive differential coefficients.
IEEE Trans. Signal Process., 2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Computation sharing programmable FIR filter for lowpower and highperformance applications.
IEEE J. Solid State Circuits, 2004
IEEE Des. Test Comput., 2004
IEEE Des. Test Comput., 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 34th IEEE International Symposium on MultipleValued Logic (ISMVL 2004), 2004
Lowpower carryselect adder using adaptive supply voltage based on input vector patterns.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Dataretention flipflops for powerdown applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Dualedge triggered level converting flipflops.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Effectiveness of energy recovery techniques in reducing onchip power density in molecular nanotechnologies.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 10th IEEE International OnLine Testing Symposium (IOLTS 2004), 2004
Proceedings of the 10th IEEE International OnLine Testing Symposium (IOLTS 2004), 2004
A Novel Bitstream Level Joint Channel Error Concealment Scheme for Realtime Video over Wireless Networks.
Proceedings of the Proceedings IEEE INFOCOM 2004, 2004
FloorplanAware LowComplexity Digital Filter Synthesis for LowPower & HighSpeed.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies.
Proceedings of the 2004 International Conference on ComputerAided Design, 2004
Proceedings of the 2004 International Conference on ComputerAided Design, 2004
Hardware architecture and VLSI implementation of a lowpower highperformance polyphase channelizer with applications to subband adaptive filtering.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
A low power reconfigurable DCT architecture to trade off image quality for computational complexity.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Proceedings of the 19th IEEE International Symposium on Defect and FaultTolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 2004 Design, 2004
Novel sizing algorithm for yield improvement under process variation in nanometer technology.
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
Estimation of delay variations due to randomdopant fluctuations in nanoscaled CMOS circuits.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
Process variation in nanoscale memories: failure analysis and process tolerant architecture.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array.
Proceedings of the International Conference on Communications in Computing, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Priority assignment optimization for minimization of current surge in high performance power efficient clockgated microprocessor.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Multipleparameter CMOS IC testing with increased sensitivity for I<sub>DDQ</sub>.
IEEE Trans. Very Large Scale Integr. Syst., 2003
Two's complement computation sharing multiplier and its applications to high performance DFE.
IEEE Trans. Signal Process., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE J. Solid State Circuits, 2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
LALM: A LogicAware Layout Methodology to Enhance the Noise Immunity of Domino Circuits.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003
Optimal body bias selection for leakage improvement and process compensation over different technology generations.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Modeling and estimation of total leakage current in nanoscaled CMOS devices considering the effect of parameter variation.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A forward bodybiased lowleakage SRAM cache: device and architecture considerations.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Integrated architectural/physical planning approach for minimization of current surge in high performance clockgated microprocessors.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A noise tolerant cache design to reduce gate and subthreshold leakage in the nanometer regime.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
A logicaware layout methodology to enhance the noise immunity of domino circuits.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation.
Proceedings of the 2003 International Conference on ComputerAided Design, 2003
Proceedings of the Ninth International Symposium on HighPerformance Computer Architecture (HPCA'03), 2003
A time borrowing selectively clocked skewed logic for highperformance circuits in scaled technologies.
Proceedings of the ESSCIRC 2003, 2003
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.
Proceedings of the 18th IEEE International Symposium on Defect and FaultTolerance in VLSI Systems (DFT 2003), 2003
Selectively Clocked CMOS Logic Style for LowPower NoiseImmune Operations in Scaled Technologies.
Proceedings of the 2003 Design, 2003
MRPF: An Architectural Transformation for Synthesis of HighPerformance and LowPower Digital Filters.
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Synthesis of ApplicationSpecific HighlyEfficient MultiMode Systems for LowPower Applications.
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the Embedded Software for SoC, 2003
2002
Vertically integrated SOI circuits for lowpower and highperformance applications.
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
O<sup>2</sup>ABA: a novel highperformance predictable circuit architecture for the deep submicron era.
IEEE Trans. Very Large Scale Integr. Syst., 2002
Decoupling capacitance allocation and its application topowersupply noiseaware floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
A graph theoretic approach for synthesizing very lowcomplexityhighspeed digital filters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
J. Circuits Syst. Comput., 2002
IEEE Des. Test Comput., 2002
IEEE Des. Test Comput., 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASPDAC 2002), 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASPDAC 2002), 2002
Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the IEEE International Conference on Acoustics, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
A novel wavelet transform based transient current analysis for fault detection and localization.
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 1820 November 2002, Guam, USA, 2002
2001
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications.
VLSI Design, 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
On effective I<sub>DDQ</sub> testing of lowvoltage CMOS circuits using leakage control techniques.
IEEE Trans. Very Large Scale Integr. Syst., 2001
A novel approach to highlevel switching activity modeling with applications to lowpower DSP system synthesis.
IEEE Trans. Signal Process., 2001
IEEE J. Solid State Circuits, 2001
IEEE Des. Test Comput., 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Reducing setassociative cache energy via wayprediction and selective directmapping.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001
Power Trends and Performance Characterization of 3Dimensional Integration for Future Technology Generations.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Design and Test of Low Voltage CMOS Circuits.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 2001 International Symposium on Physical Design, 2001
Doublegate fullydepleted SOI transistors for lowpower highperformance nanoscale circuit design.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Selectively clocked skewed logic (SCSL): lowpower logic style for highperformance applications.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 7th IEEE International OnLine Testing Workshop (IOLTW 2001), 2001
CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune PrechargeEvaluate Logic.
Proceedings of the 2001 IEEE/ACM International Conference on ComputerAided Design, 2001
Decision feedback equalizer with two's complement computation sharing multiplication.
Proceedings of the IEEE International Conference on Acoustics, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
An Integrated Circuit/Architecture Approach to Reducing Leakage in DeepSubmicron HighPerformance ICaches.
Proceedings of the Seventh International Symposium on HighPerformance Computer Architecture (HPCA'01), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Exploring SOI Device Structures and Interconnect Architectures for 3Dimensional Integration.
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 1921 November 2001, Kyoto, Japan, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Des. Test Comput., 2000
Estimation of Switching Noise on Power Supply Lines in Deep Submicron CMOS Circuits.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
GatedV<sub>dd</sub>: a circuit technique to reduce leakage in deepsubmicron cache memories
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the 6th IEEE International OnLine Testing Workshop (IOLTW 2000), 2000
Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep SubMicron CMOS Circuits.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
HighPerformance LowPower CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 2000 IEEE/ACM International Conference on ComputerAided Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on ComputerAided Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on ComputerAided Design, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Minimally redundant parallel implementation of digital filters and vector scaling.
Proceedings of the IEEE International Conference on Acoustics, 2000
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Power minimization by simultaneous dualV<sub>th</sub> assignment and gatesizing.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
A novel highperformance predictable circuit architecture for the deep submicron era.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Wiley, ISBN: 9780471114888, 2000
1999
Design and optimization of dualthreshold circuits for lowvoltage lowpower applications.
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
A Graph Theoretic Approach for Design and Synthesis of Multiplierless FIR Filters.
Proceedings of the 12th International Symposium on System Synthesis, 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design.
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on ComputerAided Design, 1999
Highlevel modeling of switching activity with application to lowpower DSP system synthesis.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction.
Proceedings of the 14th International Symposium on Defect and FaultTolerance in VLSI Systems (DFT '99), 1999
Mixed<i>V<sub>th</sub></i> (MVT) CMOS Circuit Design Methodology for Low Power Applications.
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
VLSI Design, 1998
Maximum power estimation for CMOS circuits using deterministic and statistical approaches.
IEEE Trans. Very Large Scale Integr. Syst., 1998
LVDCSL: a high fanin, highperformance, lowvoltage differential current switch logic family.
IEEE Trans. Very Large Scale Integr. Syst., 1998
Efficient statistical approach to estimate power considering uncertain properties of primary inputs.
IEEE Trans. Very Large Scale Integr. Syst., 1998
Integr. Comput. Aided Eng., 1998
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
Estimation of power sensitivity in sequential circuits with power macromodeling application.
Proceedings of the 1998 IEEE/ACM International Conference on ComputerAided Design, 1998
IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLSVLSI '98), 1998
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits.
Proceedings of the 35th Conference on Design Automation, 1998
Proceedings of the 35th Conference on Design Automation, 1998
Estimation of average switching power under accurate modeling of signal correlations.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1997
ACM Trans. Design Autom. Electr. Syst., 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Networkbased simulation laboratories for microelectronics systems design and education.
Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
LVDCSL: low voltage differential current switch logic, a robust low power DCSL family.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Estimation of Maximum Power for Sequential Circuits Considering Spurious Transitions.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits.
Proceedings of the 1997 IEEE/ACM International Conference on ComputerAided Design, 1997
Optimizing computations in a transposed direct form realization of floatingpoint LTIFIR systems.
Proceedings of the 1997 IEEE/ACM International Conference on ComputerAided Design, 1997
Power sensitivity  a new method to estimate power dissipation considering uncertain specifications of primary inputs.
Proceedings of the 1997 IEEE/ACM International Conference on ComputerAided Design, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the ASPDAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
ACM Trans. Design Autom. Electr. Syst., 1996
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE J. Solid State Circuits, 1996
Maximum power estimation for CMOS circuits using deterministic and statistic approaches.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
1995
IEEE Trans. Computers, 1995
Circuit optimization for minimisation of power consumption under delay constraint.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Estimation of sequential circuit activity considering spatial and temporal correlations.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Proceedings of the 1995 IEEE/ACM International Conference on ComputerAided Design, 1995
1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
Guest Editors' Introduction: LowPower VLSI Design.
IEEE Des. Test Comput., 1994
ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Estimation of circuit activity considering signal correlations and simultaneous switching.
Proceedings of the 1994 IEEE/ACM International Conference on ComputerAided Design, 1994
Proceedings of the FieldProgrammable Logic, 1994
Proceedings of the FieldProgrammable Logic, 1994
Logic synthesis for reliability  an early start to controlling electromigration and hot carrier effects.
Proceedings of the Proceedings EURODAC'94, 1994
1993
IEEE Trans. Very Large Scale Integr. Syst., 1993
A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Channel Architecture Optimization for Performance and Routability of RowBased FPGAs.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
1990
IEEE Trans. Computers, 1990
Proceedings of the European Design Automation Conference, 1990
1989
Proceedings of the 1989 IEEE International Conference on ComputerAided Design, 1989
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989
1988
An evaluation of systemlevel fault tolerance on the Intel hypercube multiprocessor.
Proceedings of the Eighteenth International Symposium on FaultTolerant Computing, 1988