Michael Moreinis

According to our database, Michael Moreinis authored at least 4 papers between 2003 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2006

Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.

Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny

IEEE Trans. Very Large Scale Integr. Syst., 2006

2004

Asynchronous gate-diffusion-input (GDI) circuits.

Arkadiy Morgenshtein, Michael Moreinis, Ran Ginosar

IEEE Trans. Very Large Scale Integr. Syst., 2004

Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization.

Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003

Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects.

Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny

Proceedings of the IFIP VLSI-SoC 2003, 2003