Avinoam Kolodny

According to our database, Avinoam Kolodny authored at least 100 papers between 2003 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2019

Links as a Service (LaaS): Guaranteed Tenant Isolation in the Shared Cloud.

Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy

IEEE J. Sel. Areas Commun., 2019

2017

Optimizing Read-Once Data Flow in Big-Data Applications.

Tomer Y. Morad, Gil Shomron, Mattan Erez, Avinoam Kolodny, Uri C. Weiser

IEEE Comput. Archit. Lett., 2017

2016

Design and dynamic management of hierarchical NoCs.

Ran Manevich, Israel Cidon, Avinoam Kolodny

Microprocess. Microsystems, 2016

EFS: Energy-Friendly Scheduler for memory bandwidth constrained systems.

Tomer Y. Morad, Noam Shalev, Idit Keidar, Avinoam Kolodny, Uri C. Weiser

J. Parallel Distributed Comput., 2016

2015

Multistate Register Based on Resistive RAM.

Ravi Patel, Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny

IEEE Trans. Very Large Scale Integr. Syst., 2015

Heterogeneous NoC Router Architecture.

Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny, Michael Shabun, Nir Shmuel

IEEE Trans. Parallel Distributed Syst., 2015

Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training.

Daniel Soudry, Dotan Di Castro, Asaf Gal, Avinoam Kolodny, Shahar Kvatinsky

IEEE Trans. Neural Networks Learn. Syst., 2015

VTEAM: A General Model for Voltage-Controlled Memristors.

Shahar Kvatinsky, Misbah Ramadan, Eby G. Friedman, Avinoam Kolodny

IEEE Trans. Circuits Syst. II Express Briefs, 2015

Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing.

Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny

Integr., 2015

Average latency and link utilization analysis of heterogeneous wormhole NoCs.

Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny

Integr., 2015

Links as a Service (LaaS): Feeling Alone in the Shared Cloud.

Eitan Zahavi, Alexander Shpiner, Ori Rottenstreich, Avinoam Kolodny, Isaac Keslassy

CoRR, 2015

2014

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies.

Shahar Kvatinsky, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser

IEEE Trans. Very Large Scale Integr. Syst., 2014

MAGIC - Memristor-Aided Logic.

Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Logic operations in memory using a memristive Akers array.

Yifat Levy, Jehoshua Bruck, Yuval Cassuto, Eby G. Friedman, Avinoam Kolodny, Eitan Yaakobi, Shahar Kvatinsky

Microelectron. J., 2014

Designing single-cycle long links in hierarchical NoCs.

Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny

Microprocess. Microsystems, 2014

Distributed Adaptive Routing Convergence to Non-Blocking DCN Routing Assignments.

Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny

IEEE J. Sel. Areas Commun., 2014

Memristor-Based Multithreading.

Shahar Kvatinsky, Yuval H. Nacson, Yoav Etsion, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser

IEEE Comput. Archit. Lett., 2014

Quasi Fat Trees for HPC Clouds and Their Fault-Resilient Closed-Form Routing.

Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny

Proceedings of the 22nd IEEE Annual Symposium on High-Performance Interconnects, 2014

2013

Gana: A novel low-cost conflict-free NoC architecture.

Eitan Zahavi, Israel Cidon, Avinoam Kolodny

ACM Trans. Embed. Comput. Syst., 2013

TEAM: ThrEshold Adaptive Memristor Model.

Shahar Kvatinsky, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks.

Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman

Integr., 2013

ViLoCoN - An ultra-lightweight lossless VLSI video codec.

Shani Rehana, Or Turgeman, Ran Manevich, Avinoam Kolodny

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

Dynamic traffic distribution among hierarchy levels in hierarchical Networks-on-Chip (NoCs).

Ran Manevich, Israel Cidon, Avinoam Kolodny

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Design Tradeoffs of Long Links in Hierarchical Tiled Networks-on-Chip.

Ran Manevich, Leon Polishuk, Israel Cidon, Avinoam Kolodny

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

Exploring the limits of GPGPU scheduling in control flow bound applications.

Roman Malits, Evgeny Bolotin, Avinoam Kolodny, Avi Mendelson

ACM Trans. Archit. Code Optim., 2012

Multi-aggressor capacitive and inductive coupling noise modeling and mitigation.

Victoria Vishnyakov, Eby G. Friedman, Avinoam Kolodny

Microelectron. J., 2012

Task Scheduling Based On Thread Essence and Resource Limitations.

Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser

J. Comput., 2012

The complexity of VLSI power-delay optimization by interconnect resizing.

Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer

J. Comb. Optim., 2012

Handling global traffic in future CMP NoCs.

Ran Manevich, Israel Cidon, Avinoam Kolodny

Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

Optimizing heterogeneous NoC design.

Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny

Proceedings of the International Workshop on System Level Interconnect Prediction, 2012

HNOCS: Modular open-source simulator for Heterogeneous NoCs.

Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Energy metrics for power efficient crosslink and mesh topologies.

Inna Vaisband, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Distributed adaptive routing for big-data applications running on data center networks.

Eitan Zahavi, Isaac Keslassy, Avinoam Kolodny

Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012

2011

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints.

Yoni Aizik, Avinoam Kolodny

VLSI Design, 2011

Static timing analysis for modeling QoS in networks-on-chip.

Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter, Mattan Erez

J. Parallel Distributed Comput., 2011

NoCs simulation framework for OMNeT++.

Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny

Proceedings of the NOCS 2011, 2011

Delay analysis of wormhole based heterogeneous NoC.

Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny

Proceedings of the NOCS 2011, 2011

An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm.

Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Memristor-based IMPLY logic design procedure.

Shahar Kvatinsky, Avinoam Kolodny, Uri C. Weiser, Eby G. Friedman

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

A Cost Effective Centralized Adaptive Routing for Networks-on-Chip.

Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study.

Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny

Proceedings of the Low Power Networks-on-Chip., 2011

2010

Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696].

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny

IEEE Trans. Very Large Scale Integr. Syst., 2010

Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect.

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny

IEEE Trans. Very Large Scale Integr. Syst., 2010

Asynchronous Current Mode Serial Communication.

Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam Kolodny, Ran Ginosar

IEEE Trans. Very Large Scale Integr. Syst., 2010

Interconnect Bundle Sizing Under Discrete Design Rules.

Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Centralized Adaptive Routing for NoCs.

Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter

IEEE Comput. Archit. Lett., 2010

Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors.

Tomer Y. Morad, Avinoam Kolodny, Uri C. Weiser

Proceedings of the Third International Symposium on Parallel Architectures, 2010

Interconnect power and delay optimization by dynamic programming in gridded design rules.

Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer

Proceedings of the 2010 International Symposium on Physical Design, 2010

Efficiency optimization of integrated DC-DC buck converters.

Gregory Sizikov, Avinoam Kolodny, Eby G. Friedman, Michael Zelikson

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Threads vs. caches: Modeling the behavior of parallel workloads.

Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser

Proceedings of the 28th International Conference on Computer Design, 2010

Performance and Power Aware CMP Thread Allocation Modeling.

Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny

Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Timing-driven variation-aware nonuniform clock mesh synthesis.

Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study.

Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny

Proceedings of the Design, Automation and Test in Europe, 2010

The Devolution of Synchronizers.

Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin, Avinoam Kolodny

Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

2009

Special Section on International Symposium on Networks-on-Chip (NOCS).

Avinoam Kolodny, Li-Shiuan Peh

IEEE Trans. Very Large Scale Integr. Syst., 2009

Power-delay optimization in VLSI microprocessors by wire spacing.

Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer

ACM Trans. Design Autom. Electr. Syst., 2009

QNoC asynchronous router.

Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny

Integr., 2009

Many-Core vs. Many-Thread Machines: Stay Away From the Valley.

Zvika Guz, Evgeny Bolotin, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser

IEEE Comput. Archit. Lett., 2009

Best of both worlds: A bus enhanced NoC (BENoC).

Ran Manevich, Isask'har Walter, Israel Cidon, Avinoam Kolodny

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Packet-level static timing analysis for NoCs.

Evgeni Krimer, Mattan Erez, Isaac Keslassy, Avinoam Kolodny, Isask'har Walter

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

The design of a latency constrained, power optimized NoC for a 4G SoC.

Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

The era of many-modules SoC: revisiting the NoC mapping problem.

Isask'har Walter, Israel Cidon, Avinoam Kolodny, Daniel Sigalov

Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Power efficient tree-based crosslinks for skew reduction.

Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Effective Radii of On-Chip Decoupling Capacitors.

Mikhail Popovich, Michael Sotman, Avinoam Kolodny, Eby G. Friedman

IEEE Trans. Very Large Scale Integr. Syst., 2008

On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits.

Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny

IEEE Trans. Very Large Scale Integr. Syst., 2008

Timing-aware power-optimal ordering of signals.

Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer

ACM Trans. Design Autom. Electr. Syst., 2008

On optimal ordering of signals in parallel wire bundles.

Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny

Integr., 2008

BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP.

Isask'har Walter, Israel Cidon, Avinoam Kolodny

IEEE Comput. Archit. Lett., 2008

Utilizing shared data in chip multiprocessors with the nahalal architecture.

Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser

Proceedings of the SPAA 2008: Proceedings of the 20th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2008

Timing optimization in logic with interconnect.

Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny

Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

Parallel vs. serial on-chip communication.

Rostislav (Reuven) Dobkin, Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar

Proceedings of the Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), 2008

2007

Network Delays and Link Capacities in Application-Specific Wormhole NoCs.

Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny

VLSI Design, 2007

Trace cache sampling filter.

Michael Behar, Avi Mendelson, Avinoam Kolodny

ACM Trans. Comput. Syst., 2007

Nahalal: Cache Organization for Chip Multiprocessors.

Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser

IEEE Comput. Archit. Lett., 2007

Networks on chips: keeping up with Rent's rule and Moore's law.

Avinoam Kolodny

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Access Regulation to Hot-Modules in Wormhole NoCs.

Isask'har Walter, Israel Cidon, Ran Ginosar, Avinoam Kolodny

Proceedings of the First International Symposium on Networks-on-Chips, 2007

The Power of Priority: NoC Based Distributed Cache Coherency.

Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Routing table minimization for irregular mesh NoCs.

Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link.

Rostislav (Reuven) Dobkin, Yevgeny Perelman, Tuvia Liran, Ran Ginosar, Avinoam Kolodny

Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

2006

Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization.

Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny

IEEE Trans. Very Large Scale Integr. Syst., 2006

Optimal bus sizing in migration of processor design.

Shmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

On-die decoupling capacitance: frequency domain analysis of activity radius.

Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.

Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Maximum effective distance of on-chip decoupling capacitors in power distribution grids.

Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Efficient link capacity and QoS design for network-on-chip.

Zvika Guz, Isask'har Walter, Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Fast Asynchronous Shift Register for Bit-Serial Communication.

Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny

Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005

Comparison of Sigma-delta Converter Circuit Architectures in Digital Cmos Technology.

Noam Dolev, Avner Kornfeld, Avinoam Kolodny

J. Circuits Syst. Comput., 2005

Low-leakage repeaters for NoC interconnects.

Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

QNoC: QoS architecture and design process for network on chip.

Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny

J. Syst. Archit., 2004

Cost considerations in network on chip.

Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam Kolodny

Integr., 2004

Interconnect-power dissipation in a microprocessor.

Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir

Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

Comparative analysis of serial vs parallel links in NoC.

Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar

Proceedings of the 2004 International Symposium on System-on-Chip, 2004

Micro-modem - reliability solution for NoC communications.

Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization.

Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Optimal resizing of bus wires in layout migration.

Shay Michaely, Shmuel Wimer, Avinoam Kolodny

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Automatic hardware-efficient SoC integration by QoS network on chip.

Evgeny Bolotin, Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

Design and modelling of network on chip interconnects using transmission lines.

Anastasia Barger, David Goren, Avinoam Kolodny

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003

Crosstalk noise reduction in synthesized digital logic circuits.

O. Milter, Avinoam Kolodny

IEEE Trans. Very Large Scale Integr. Syst., 2003

A clock-tuning circuit for system-on-chip.

Y. Elboim, Avinoam Kolodny, Ran Ginosar

IEEE Trans. Very Large Scale Integr. Syst., 2003

Logic Gates as Repeaters (LGR) for Timing Optimization of SoC Interconnects.

Arkadiy Morgenshtein, Michael Moreinis, Israel A. Wagner, Avinoam Kolodny

Proceedings of the IFIP VLSI-SoC 2003, 2003