Michael Pressler

According to our database1, Michael Pressler authored at least 11 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Fine-grained adaptive parallelism for automotive systems through AMALTHEA and OpenMP.
J. Syst. Archit., January, 2024

2022
Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores.
Proceedings of the 28th IEEE Real-Time and Embedded Technology and Applications Symposium, 2022

2021
Performance modeling of heterogeneous HW platforms.
Microprocess. Microsystems, November, 2021

Brief Industry Paper: Dissecting the QNX Adaptive Partitioning Scheduler.
Proceedings of the 27th IEEE Real-Time and Embedded Technology and Applications Symposium, 2021

2020
Applying Reservation-based Scheduling to a μC-based Hypervisor: An industrial case study.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2017
Communication Centric Design in Complex Automotive Embedded Systems.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

2015
Fast Software Performance Evaluation for Embedded Hardware in Componentbased Embedded Systems.
Proceedings of the Software Engineering & Management 2015, Multikonferenz der GI-Fachbereiche Softwaretechnik (SWT) und Wirtschaftsinformatik (WI), FA WI-MAW, 17. März, 2015

2014
Execution cost estimation for software deployment in component-based embedded systems.
Proceedings of the CBSE'14, Proceedings of the 17th International ACM SIGSOFT Symposium on Component-Based Software Engineering (part of CompArch 2014), Marcq-en-Baroeul, Lille, France, June 30, 2014

2013
Reliability assessment of safety-relevant automotive systems in a model-based design flow.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2009
White box performance analysis considering static non-preemptive software scheduling.
Proceedings of the Design, Automation and Test in Europe, 2009

Bottom-up performance analysis considering time slice based software scheduling at system level.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009


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