Daniel Mueller-Gritschneder
Orcid: 0000-0003-0903-631XAffiliations:
- TU Munich, Germany
According to our database1,
Daniel Mueller-Gritschneder
authored at least 91 papers
between 2004 and 2024.
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on orcid.org
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on dl.acm.org
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Bibliography
2024
Wino Vidi Vici: Conquering Numerical Instability of 8-bit Winograd Convolution for Accurate Inference Acceleration on Edge.
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2024
2023
SN Comput. Sci., March, 2023
EGIC: Enhanced Low-Bit-Rate Generative Image Compression Guided by Semantic Segmentation.
CoRR, 2023
CoRR, 2023
Fused Depthwise Tiling for Memory Optimization in TinyML Deep Neural Network Inference.
CoRR, 2023
Effective Processor Model Generation from Instruction Set Simulator to Hardware Design.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023
Proceedings of the 35th Euromicro Conference on Real-Time Systems, 2023
Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
vRTLmod: An LLVM based Open-source Tool to Enable Fault Injection in Verilator RTL Simulations.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors.
ACM Trans. Archit. Code Optim., 2022
IACR Cryptol. ePrint Arch., 2022
Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores.
Proceedings of the 28th IEEE Real-Time and Embedded Technology and Applications Symposium, 2022
Proceedings of the 10th International Conference on Model-Driven Engineering and Software Development, 2022
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022
CorePerfDSL: A Flexible Processor Description Language for Software Performance Simulation.
Proceedings of the Forum on Specification & Design Languages, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance.
ACM Trans. Embed. Comput. Syst., 2021
A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs.
ACM Trans. Archit. Code Optim., 2021
Int. J. Parallel Program., 2021
Learning based Memory Interference Prediction for Co-running Applications on Multi-Cores.
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021
Exploring the RISC-V Vector Extension for the Classic McEliece Post-Quantum Cryptosystem.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 20th IEEE International Conference on Machine Learning and Applications, 2021
Proceedings of the CODES/ISSS 2021, 2021
2020
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs.
ACM Trans. Design Autom. Electr. Syst., 2020
Driver Generation for IoT Nodes With Optimization of the Hardware/Software Interface.
IEEE Embed. Syst. Lett., 2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
ML Training on a Tiny Microcontroller for a Self-adaptive Neural Network-Based DC Motor Speed Controller.
Proceedings of the IoT Streams for Data-Driven Predictive Maintenance and IoT, Edge, and Mobile for Embedded Machine Learning, 2020
Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Analysis of Dissipative Losses in Modular Reconfigurable Energy Storage Systems Using SystemC TLM and SystemC-AMS.
ACM Trans. Design Autom. Electr. Syst., 2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
ACM Trans. Design Autom. Electr. Syst., 2018
ACM Trans. Embed. Comput. Syst., 2018
Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML.
Proceedings of the International Conference on Computer-Aided Design, 2018
Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 Forum on Specification & Design Languages, 2018
ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping.
Proceedings of the International Symposium on Rapid System Prototyping, 2017
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017
2016
Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models.
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
2015
it Inf. Technol., 2015
Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip.
Proceedings of the Ninth International Workshop on Interconnection Network Architectures: On-Chip, 2015
The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab., 2014
System C-based multi-level error injection for the evaluation of fault-tolerant systems.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
IEEE Micro, 2013
Proceedings of the IEEE International Systems Conference, 2013
A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot.
Proceedings of the Design, Automation and Test in Europe, 2013
Analytical timing estimation for temporally decoupled TLMs considering resource conflicts.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
Automated construction of a cycle-approximate transaction level model of a memory controller.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Accurately timed transaction level models for virtual prototyping at high abstraction level.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems.
SIAM J. Optim., 2009
Int. J. Circuit Theory Appl., 2009
2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A CPPLL hierarchical optimization methodology considering jitter, power and locking time.
Proceedings of the 43rd Design Automation Conference, 2006
2005
Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
IEEE Trans. Instrum. Meas., 2004