Daniel Mueller-Gritschneder

According to our database1, Daniel Mueller-Gritschneder authored at least 54 papers between 2004 and 2019.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2019
Analysis of Dissipative Losses in Modular Reconfigurable Energy Storage Systems Using SystemC TLM and SystemC-AMS.
ACM Trans. Design Autom. Electr. Syst., 2019

Fully Distributed Deep Learning Inference on Resource-Constrained Edge Devices.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Instruction Extension of a RISC-V Processor Modeled with IP-XACT.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

SRAM Design Exploration with Integrated Application-Aware Aging Analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Towards Reliable and Secure Post-Quantum Co-Processors based on RISC-V.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

ACCESS: HW/SW Co-Equivalence Checking for Firmware Optimization.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs.
ACM Trans. Design Autom. Electr. Syst., 2018

Fault Injection for Test-Driven Development of Robust SoC Firmware.
ACM Trans. Embedded Comput. Syst., 2018

Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML.
Proceedings of the International Conference on Computer-Aided Design, 2018

Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search.
Proceedings of the International Conference on Computer-Aided Design, 2018

Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Design and validation of fault-tolerant embedded controllers.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Host-Compiled Simulation.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

Model-based framework for networks-on-chip design space exploration.
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017

2016
Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models.
Proceedings of the International Symposium on Integrated Circuits, 2016

Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015
Application-aware cross-layer reliability analysis and optimization.
it - Information Technology, 2015

Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip.
Proceedings of the Ninth International Workshop on Interconnection Network Architectures: On-Chip, 2015

The next generation of virtual prototyping: ultra-fast yet accurate simulation of HW/SW systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectronics Reliability, 2014

System C-based multi-level error injection for the evaluation of fault-tolerant systems.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Fault-tolerant embedded control systems for unreliable hardware.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014


2013
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience.
IEEE Micro, 2013

Application of Dempster-Shafer Theory to task mapping under epistemic uncertainty.
Proceedings of the IEEE International Systems Conference, 2013

A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

A spectral clustering approach to application-specific network-on-chip synthesis.
Proceedings of the Design, Automation and Test in Europe, 2013

A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot.
Proceedings of the Design, Automation and Test in Europe, 2013

Analytical timing estimation for temporally decoupled TLMs considering resource conflicts.
Proceedings of the Design, Automation and Test in Europe, 2013

Fast cache simulation for host-compiled simulation of embedded software.
Proceedings of the Design, Automation and Test in Europe, 2013

Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Hierarchical control flow matching for source-level simulation of embedded software.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Automated construction of a cycle-approximate transaction level model of a memory controller.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Accurately timed transaction level models for virtual prototyping at high abstraction level.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems.
SIAM Journal on Optimization, 2009

Pareto optimization of analog circuits considering variability.
I. J. Circuit Theory and Applications, 2009

2007
Pareto-Front Computation and Automatic Sizing of CPPLLs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A CPPLL hierarchical optimization methodology considering jitter, power and locking time.
Proceedings of the 43rd Design Automation Conference, 2006

2004
Signal processing strategies with the TDEMI measurement system.
IEEE Trans. Instrumentation and Measurement, 2004


  Loading...