Ulf Schlichtmann
Orcid: 0000-0003-4431-7619Affiliations:
- Technical University of Munich, Institute for Electronic Design Automation, Germany
According to our database1,
Ulf Schlichtmann
authored at least 312 papers
between 1991 and 2024.
Collaborative distances:
Collaborative distances:
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Online presence:
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on d-nb.info
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On csauthors.net:
Bibliography
2024
CorrectNet+: Dealing With HW Non-Idealities in In-Memory-Computing Platforms by Error Suppression and Compensation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
Control-Logic Synthesis of Fully Programmable Valve Array Using Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
EncodingNet: A Novel Encoding-based MAC Design for Efficient Neural Network Acceleration.
CoRR, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023
Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
ACM Trans. Design Autom. Electr. Syst., March, 2023
IEEE Des. Test, February, 2023
IEEE Des. Test, February, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation.
CoRR, 2023
CoRR, 2023
Expressivity Enhancement with Efficient Quadratic Neurons for Convolutional Neural Networks.
CoRR, 2023
Fused Depthwise Tiling for Memory Optimization in TinyML Deep Neural Network Inference.
CoRR, 2023
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023
Implementation of a Robust and Power-Efficient Nonlinear 64-QAM Demapper using In-Memory Computing.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
FXT-Route: Efficient High-Performance PCB Routing with Crosstalk Reduction Using Spiral Delay Lines.
Proceedings of the 2023 International Symposium on Physical Design, 2023
ARMM: Adaptive Reliability Quantification Model of Microfluidic Designs and its Graph-Transformer-Based Implementation.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
A Novel and Efficient Block-Based Programming for ReRAM-Based Neuromorphic Computing.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023
SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the 35th Euromicro Conference on Real-Time Systems, 2023
An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
XRing: A Crosstalk-Aware Synthesis Method for Wavelength-Routed Optical Ring Routers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
PowerPruning: Selecting Weights and Activations for Power-Efficient Neural Network Acceleration.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Flow-Based Microfluidic Biochips With Distributed Channel Storage: Synthesis, Physical Design, and Wash Optimization.
IEEE Trans. Computers, 2022
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors.
ACM Trans. Archit. Code Optim., 2022
ACM Comput. Surv., 2022
Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores.
Proceedings of the 28th IEEE Real-Time and Embedded Technology and Applications Symposium, 2022
Proceedings of the 11th Mediterranean Conference on Embedded Computing, 2022
A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
CoMUX: Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer Design.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
CorePerfDSL: A Flexible Processor Description Language for Software Performance Simulation.
Proceedings of the Forum on Specification & Design Languages, 2022
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the IEEE European Test Symposium, 2022
RRAM-based Neuromorphic Computing: Data Representation, Architecture, Logic, and Programming.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
Contamination-Free Switch Design and Synthesis for Microfluidic Large-Scale Integration.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Differentially Evolving Memory Ensembles: Pareto Optimization based on Computational Intelligence for Embedded Memories on a System Level.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
REPAIR: Control Flow Protection based on Register Pairing Updates for SW-Implemented HW Fault Tolerance.
ACM Trans. Embed. Comput. Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
A Distributed Hardware Monitoring System for Runtime Verification on Multi-Tile MPSoCs.
ACM Trans. Archit. Code Optim., 2021
Int. J. Parallel Program., 2021
IEEE Des. Test, 2021
Learning based Memory Interference Prediction for Co-running Applications on Multi-Cores.
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021
Feeding Hungry Models Less: Deep Transfer Learning for Embedded Memory PPA Models : Special Session.
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021
A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators.
Proceedings of the IEEE International Test Conference, 2021
RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-Chip.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Manufacturing Cycle-Time Optimization Using Gaussian Drying Model for Inkjet-Printed Electronics.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip Systems.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware Training.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Hardware-Software Codesign of Weight Reshaping and Systolic Array Multiplexing for Efficient CNNs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
FAST: A Fast Automatic Sweeping Topology Customization Method for Application-Specific Wavelength-Routed Optical NoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
ACM Trans. Design Autom. Electr. Syst., 2020
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs.
ACM Trans. Design Autom. Electr. Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Integr., 2020
Driver Generation for IoT Nodes With Optimization of the Hardware/Software Interface.
IEEE Embed. Syst. Lett., 2020
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix).
CoRR, 2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Partial Sharing Neural Networks for Multi-Target Regression on Power and Performance of Embedded Memories.
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020
Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors.
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
PSION 2: Optimizing Physical Layout of Wavelength-Routed ONoCs for Laser Power Reduction.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
PathDriver: A Path-Driven Architectural Synthesis Flow for Continuous-Flow Microfluidic Biochips.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and Noise.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Investigating the Inherent Soft Error Resilience of Embedded Applications by Full-System Simulation.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Maximizing the Communication Parallelism for Wavelength-Routed Optical Networks-On-Chips.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (Dagstuhl Seminar 19152).
Dagstuhl Reports, 2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
MAGIC: A Wear-leveling Circuitry to Mitigate Aging Effects in Sense Amplifiers of SRAMs.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
A Compact Model of Negative Bias Temperature Instability Suitable for Gate-Level Circuit Simulation.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Wavelength-Routed Optical NoCs: Design and EDA - State of the Art and Future Directions: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
Cloud Columba: Accessible Design Automation Platform for Production and Inspiration: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
VOM: Flow-Path Validation and Control-Sequence Optimization for Multilayered Continuous-Flow Microfluidic Biochips.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Block-Flushing: A Block-based Washing Algorithm for Programmable Microfluidic Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Physical Synthesis of Flow-Based Microfluidic Biochips Considering Distributed Channel Storage.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control Ports.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
ACM Trans. Design Autom. Electr. Syst., 2018
ACM Trans. Embed. Comput. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices.
Microelectron. J., 2018
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era.
IPSJ Trans. Syst. LSI Des. Methodol., 2018
Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips.
Proceedings of the International Conference on Computer-Aided Design, 2018
Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML.
Proceedings of the International Conference on Computer-Aided Design, 2018
CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs.
Proceedings of the International Conference on Computer-Aided Design, 2018
Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 Forum on Specification & Design Languages, 2018
Proceedings of the 2018 Forum on Specification & Design Languages, 2018
An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis.
Proceedings of the 23rd IEEE European Test Symposium, 2018
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units.
Proceedings of the 55th Annual Design Automation Conference, 2018
Columba S: a scalable co-layout design automation tool for microfluidic large-scale integration.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Biomed. Circuits Syst., 2017
Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping.
Microprocess. Microsystems, 2017
Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers.
CoRR, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
20nm FinFET-based SRAM cell: Impact of variability and design choices on performance characteristics.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping.
Proceedings of the International Symposium on Rapid System Prototyping, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs).
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage.
Proceedings of the 54th Annual Design Automation Conference, 2017
Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling.
Proceedings of the 54th Annual Design Automation Conference, 2017
Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
FinFET-based product performance: Modeling and evaluation of standard cells in FinFET technologies.
Microelectron. Reliab., 2016
PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer.
ACM J. Emerg. Technol. Comput. Syst., 2016
it Inf. Technol., 2016
Efficient handling of the fault space in functional safety analysis utilizing formal methods.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 2016 IEEE International Conference on Smart Grid Communications, 2016
Proceedings of the 13th International Conference on Synthesis, 2016
Proceedings of the 2016 on International Symposium on Physical Design, 2016
Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models.
Proceedings of the International Symposium on Integrated Circuits, 2016
PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the Second International Conference on Event-based Control, 2016
Sampling-based buffer insertion for post-silicon yield improvement under process variability.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016
Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
ACM J. Emerg. Technol. Comput. Syst., 2015
it Inf. Technol., 2015
IEEE Des. Test, 2015
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the Trust and Trustworthy Computing - 8th International Conference, 2015
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip.
Proceedings of the Ninth International Workshop on Interconnection Network Architectures: On-Chip, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Microelectron. Reliab., 2014
A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits.
Microelectron. Reliab., 2014
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
An Analysis of Industrial SRAM Test Results - A Comprehensive Study on Effectiveness and Classification of March Test Algorithms.
IEEE Des. Test, 2014
Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC Computing Architecture.
CoRR, 2014
System C-based multi-level error injection for the evaluation of fault-tolerant systems.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Connecting different worlds - Technology abstraction for reliability-aware design and Test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Probabilistic standard cell modeling considering non-Gaussian parameters and correlations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Micro, 2013
Proceedings of the IEEE International Systems Conference, 2013
A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
Post-route alleviation of dense meander segments in high-performance printed circuit boards.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Post-route refinement for high-frequency PCBs considering meander segment alleviation.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot.
Proceedings of the Design, Automation and Test in Europe, 2013
Analytical timing estimation for temporally decoupled TLMs considering resource conflicts.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Reliability challenges for electric vehicles: from devices to architecture and systems software.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Microelectron. Reliab., 2012
Microelectron. Reliab., 2012
IET Circuits Devices Syst., 2012
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012
Proceedings of the 2012 International Symposium on System on Chip, 2012
Automated construction of a cycle-approximate transaction level model of a memory controller.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Accurately timed transaction level models for virtual prototyping at high abstraction level.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012
2011
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the HOST 2011, 2011
Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
2010
Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene).
it Inf. Technol., 2010
White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the 2010 International Symposium on Physical Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2009
A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems.
SIAM J. Optim., 2009
Int. J. Circuit Theory Appl., 2009
IACR Cryptol. ePrint Arch., 2009
On-Chip Electric Waves: An Analog Circuit Approach to Physical Uncloneable Functions.
IACR Cryptol. ePrint Arch., 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Sensitivity based parameter reduction for statistical analysis of circuit performance.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
Digital design at a crossroads How to make statistical design methodologies industrially relevant.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009
2008
Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Proceedings of the 2008 International Symposium on Physical Design, 2008
A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters.
Proceedings of the 26th International Conference on Computer Design, 2008
Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
A CPPLL hierarchical optimization methodology considering jitter, power and locking time.
Proceedings of the 43rd Design Automation Conference, 2006
2005
Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005
Proceedings of the 42nd Design Automation Conference, 2005
2004
Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
Proceedings of the Ultra Low-Power Electronics and Design, 2004
2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002
Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs.
Proceedings of the 2002 Design, 2002
1999
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs.
ACM Trans. Design Autom. Electr. Syst., 1999
1996
1995
PhD thesis, 1995
1994
A new power estimation technique with application to decomposition of Boolean functions for low power.
Proceedings of the Proceedings EURO-DAC'94, 1994
1992
Proceedings of the 29th Design Automation Conference, 1992
1991
Proceedings of the conference on European design automation, 1991