Ulf Schlichtmann

According to our database1, Ulf Schlichtmann authored at least 193 papers between 1991 and 2018.

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Bibliography

2018
Automated Phase-Noise-Aware Design of RF Clock Distribution Circuits.
IEEE Trans. VLSI Syst., 2018

Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs.
ACM Trans. Design Autom. Electr. Syst., 2018

Fault Injection for Test-Driven Development of Robust SoC Firmware.
ACM Trans. Embedded Comput. Syst., 2018

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Efficient spanning-tree-based test pattern generation for Programmable Microfluidic Devices.
Microelectronics Journal, 2018

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era.
IPSJ Trans. System LSI Design Methodology, 2018

Timing with Virtual Signal Synchronization for Circuit Performance and Netlist Security.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018

Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips.
Proceedings of the International Conference on Computer-Aided Design, 2018

Performance and accuracy in soft-error resilience evaluation using the multi-level processor simulator ETISS-ML.
Proceedings of the International Conference on Computer-Aided Design, 2018

CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs.
Proceedings of the International Conference on Computer-Aided Design, 2018

Wavefront-MCTS: multi-objective design space exploration of NoC architectures based on Monte Carlo tree search.
Proceedings of the International Conference on Computer-Aided Design, 2018

Automatic Design of Microfluidic Devices.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis.
Proceedings of the 23rd IEEE European Test Symposium, 2018

TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay units.
Proceedings of the 55th Annual Design Automation Conference, 2018

Columba S: a scalable co-layout design automation tool for microfluidic large-scale integration.
Proceedings of the 55th Annual Design Automation Conference, 2018

Design-for-testability for continuous-flow microfluidic biochips.
Proceedings of the 55th Annual Design Automation Conference, 2018

PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip.
Proceedings of the 55th Annual Design Automation Conference, 2018

On enabling diagnosis for 1-Pin Test fails in an industrial flow.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips.
IEEE Trans. Biomed. Circuits and Systems, 2017

Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model.
CoRR, 2017

EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers.
CoRR, 2017

Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability.
CoRR, 2017

Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning.
CoRR, 2017

Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing.
CoRR, 2017

Storage and Caching: Synthesis of Flow-based Microfluidic Biochips.
CoRR, 2017

ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing.
CoRR, 2017

Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards.
CoRR, 2017

Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation.
CoRR, 2017

Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage.
CoRR, 2017

Testing Microfluidic Fully Programmable Valve Arrays (FPVAs).
CoRR, 2017

Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements.
CoRR, 2017

Static Timing Model Extraction for Combinational Circuits.
CoRR, 2017

On Timing Model Extraction and Hierarchical Statistical Timing Analysis.
CoRR, 2017

On Hierarchical Statistical Static Timing Analysis.
CoRR, 2017

Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations.
CoRR, 2017

Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers.
CoRR, 2017

Timing Model Extraction for Sequential Circuits Considering Process Variations.
CoRR, 2017

Application of machine learning methods in post-silicon yield improvement.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Generative adversarial network based scalable on-chip noise sensor placement.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

20nm FinFET-based SRAM cell: Impact of variability and design choices on performance characteristics.
Proceedings of the 14th International Conference on Synthesis, 2017

Frontiers of timing.
Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

Methodology for automated phase noise minimization in RF circuit interconnect trees.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Model-based framework for networks-on-chip design space exploration.
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017

A Method for Phase Noise Analysis of RF Circuits.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs).
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Testing microfluidic Fully Programmable Valve Arrays (FPVAs).
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage.
Proceedings of the 54th Annual Design Automation Conference, 2017

Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling.
Proceedings of the 54th Annual Design Automation Conference, 2017

Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

FinFET-based product performance: Modeling and evaluation of standard cells in FinFET technologies.
Microelectronics Reliability, 2016

Editorial.
Microelectronics Reliability, 2016

PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer.
JETC, 2016

Dark silicon management: an integrated and coordinated cross-layer approach.
it - Information Technology, 2016

Efficient handling of the fault space in functional safety analysis utilizing formal methods.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

On the measurement of power grid robustness under load uncertainties.
Proceedings of the 2016 IEEE International Conference on Smart Grid Communications, 2016

Synthesis-based methodology for high-speed multi-modulus divider.
Proceedings of the 13th International Conference on Synthesis, 2016

PLATON: A Force-Directed Placement Algorithm for 3D Optical Networks-on-Chip.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

Safety evaluation based on virtual prototypes: Fault injection with multi-level processor models.
Proceedings of the International Symposium on Integrated Circuits, 2016

PieceTimer: a holistic timing analysis framework considering setup/hold time interdependency using a piecewise model.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

From biochips to quantum circuits: computer-aided design for emerging technologies.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Control-fluidic CoDesign for paper-based digital microfluidic biochips.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Where formal verification can help in functional safety analysis.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Hardware-Accelerated Software Library Drivers Generation for IP-Centric SoC Designs.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Sampling-based buffer insertion for post-silicon yield improvement under process variability.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Sieve-valve-aware synthesis of flow-based microfluidic biochips considering specific biological execution limitations.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

EffiTest: efficient delay test and statistical prediction for configuring post-silicon tunable buffers.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Columba: co-layout synthesis for continuous-flow microfluidic biochips.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Fault injection at host-compiled level with static fault set reduction for SoC firmware robustness testing.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Reliability, adaptability and flexibility in timing: Buy a life insurance for your circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

A Cross-Layer Approach to Measure the Robustness of Integrated Circuits.
JETC, 2015

Application-aware cross-layer reliability analysis and optimization.
it - Information Technology, 2015

Storage and Caching: Synthesis of Flow-Based Microfluidic Biochips.
IEEE Design & Test, 2015

Integrating aging aware timing analysis into a commercial STA tool.
Proceedings of the VLSI Design, Automation and Test, 2015

MWA Skew SRAM Based SIMPL Systems for Public-Key Physical Cryptography.
Proceedings of the Trust and Trustworthy Computing - 8th International Conference, 2015

Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Emulation of an ASIC power and temperature monitor system for FPGA prototyping.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Beyond GORDIAN and Kraftwerk: EDA Research at TUM.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip.
Proceedings of the Ninth International Workshop on Interconnection Network Architectures: On-Chip, 2015

Timing verification for adaptive integrated circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Reliability-aware synthesis for flow-based microfluidic biochips by dynamic-device mapping.
Proceedings of the 52nd Annual Design Automation Conference, 2015

GRIP: grammar-based IP integration and packaging for acceleration-rich SoC designs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Monitoring of aging in integrated circuits by identifying possible critical paths.
Microelectronics Reliability, 2014

A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits.
Microelectronics Reliability, 2014

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectronics Reliability, 2014

Robustness measurement of integrated circuits and its adaptation to aging effects.
Microelectronics Reliability, 2014

Special section reliability and variability of devices for circuits and systems.
Microelectronics Reliability, 2014

An Analysis of Industrial SRAM Test Results - A Comprehensive Study on Effectiveness and Classification of March Test Algorithms.
IEEE Design & Test, 2014

Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC Computing Architecture.
CoRR, 2014

System C-based multi-level error injection for the evaluation of fault-tolerant systems.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Fault-tolerant embedded control systems for unreliable hardware.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Connecting different worlds - Technology abstraction for reliability-aware design and Test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Special session: How secure are PUFs really? On the reach and limits of recent PUF attacks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Probabilistic standard cell modeling considering non-Gaussian parameters and correlations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
On Timing Model Extraction and Hierarchical Statistical Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience.
IEEE Micro, 2013

Application of Dempster-Shafer Theory to task mapping under epistemic uncertainty.
Proceedings of the IEEE International Systems Conference, 2013

A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

Post-route alleviation of dense meander segments in high-performance printed circuit boards.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

PROTON: an automatic place-and-route tool for optical networks-on-chip.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Post-route refinement for high-frequency PCBs considering meander segment alleviation.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

A spectral clustering approach to application-specific network-on-chip synthesis.
Proceedings of the Design, Automation and Test in Europe, 2013

A virtual prototyping platform for real-time systems with a case study for a two-wheeled robot.
Proceedings of the Design, Automation and Test in Europe, 2013

Analytical timing estimation for temporally decoupled TLMs considering resource conflicts.
Proceedings of the Design, Automation and Test in Europe, 2013

Fast cache simulation for host-compiled simulation of embedded software.
Proceedings of the Design, Automation and Test in Europe, 2013

Predicting future product performance: modeling and evaluation of standard cells in FinFET technologies.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Reliability challenges for electric vehicles: from devices to architecture and systems software.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Memory access reconstruction based on memory allocation mechanism for source-level simulation of embedded software.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Efficiently analyzing the impact of aging effects on large integrated circuits.
Microelectronics Reliability, 2012

ICMAT 2011 - Reliability and variability of semiconductor devices and ICs.
Microelectronics Reliability, 2012

Iterative timing analysis based on nonlinear and interdependent flipflop modelling.
IET Circuits, Devices & Systems, 2012

Schedulability Analysis for Processors with Aging-Aware Autonomic Frequency Scaling.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Hierarchical control flow matching for source-level simulation of embedded software.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Automated construction of a cycle-approximate transaction level model of a memory controller.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Accurately timed transaction level models for virtual prototyping at high abstraction level.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Current source modeling for power and timing analysis at different supply voltages.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Characterization of the bistable ring PUF.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Circuit-Based Approaches to Simpl Systems.
Journal of Circuits, Systems, and Computers, 2011

Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Iterative Timing Analysis Considering Interdependency of Setup and Hold Times.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Timing Modeling of Flipflops Considering Aging Effects.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions.
Proceedings of the HOST 2011, 2011

Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011


2010
Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level (Alterungsanalyse von kombinatorischen Schaltungen auf Gatterebene).
it - Information Technology, 2010

Towards Electrical, Integrated Implementations of SIMPL Systems.
Proceedings of the Information Security Theory and Practices. Security and Privacy of Pervasive Systems and Smart Devices, 2010

White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Automatic generation of hierarchical placement rules for analog integrated circuits.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Aging analysis at gate and macro cell level.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Fast statistical timing analysis of latch-controlled circuits for arbitrary clock periods.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009
A Successive Approach to Compute the Bounded Pareto Front of Practical Multiobjective Optimization Problems.
SIAM Journal on Optimization, 2009

Pareto optimization of analog circuits considering variability.
I. J. Circuit Theory and Applications, 2009

Towards Electrical, Integrated Implementations of SIMPL Systems.
IACR Cryptology ePrint Archive, 2009

On-Chip Electric Waves: An Analog Circuit Approach to Physical Uncloneable Functions.
IACR Cryptology ePrint Archive, 2009

Aging analysis of circuit timing considering NBTI and HCI.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Sensitivity based parameter reduction for statistical analysis of circuit performance.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Timing model extraction for sequential circuits considering process variations.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Digital design at a crossroads How to make statistical design methodologies industrially relevant.
Proceedings of the Design, Automation and Test in Europe, 2009

On hierarchical statistical static timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2009

Fast and waveform independent characterization of current source models.
Proceedings of the 2009 IEEE International Behavioral Modeling and Simulation Workshop, 2009

2008
Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Static Timing Model Extraction for Combinational Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Abacus: fast legalization of standard cell circuits with minimal movement.
Proceedings of the 2008 International Symposium on Physical Design, 2008

A random and pseudo-gradient approach for analog circuit sizing with non-uniformly discretized parameters.
Proceedings of the 26th International Conference on Computer Design, 2008

Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Sizing Rules for Bipolar Analog Circuit Design.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Pareto-Front Computation and Automatic Sizing of CPPLLs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Optimization of SC ΣΔ modulators based on worst-case-aware Pareto-optimal fronts.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Fast evaluation of analog circuit structures by polytopal approximations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A CPPLL hierarchical optimization methodology considering jitter, power and locking time.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Eigenschaftsraumexploration bei der hierarchischen Dimensionierung analoger integrierter Schaltungen.
Proceedings of the INFORMATIK 2005, 2005

Deterministic approaches to analog performance space exploration (PSE).
Proceedings of the 42nd Design Automation Conference, 2005

2004
Design Methodology Innovations Address Manufacturing Technology Challenges: Power and Performance.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Extremely Low-Power Logic.
Proceedings of the 2004 Design, 2004

2002
Tomorrows High-Quality SoCs Require High-Quality Embedded Memories Today.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Power Crisis in SoC Design: Strategies for Constructing Low-Power, High-Performance SoC Designs.
Proceedings of the 2002 Design, 2002

1999
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs.
ACM Trans. Design Autom. Electr. Syst., 1999

1996
Fast Power Estimation of Large Circuits.
IEEE Design & Test of Computers, 1996

1995
Logiksynthese für komplexe anwenderprogrammierbare elektronische Bausteine.
PhD thesis, 1995

1994
A new power estimation technique with application to decomposition of Boolean functions for low power.
Proceedings of the Proceedings EURO-DAC'94, 1994

1992
Characterization of Boolean Functions for Rapid Matching in FPGA Technology Mapping.
Proceedings of the 29th Design Automation Conference, 1992

1991
Goal oriented slicing enumeration through shape function clipping.
Proceedings of the conference on European design automation, 1991


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