Michael Ruegg
According to our database1,
Michael Ruegg
authored at least 9 papers
between 2005 and 2012.
Collaborative distances:
Collaborative distances:
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Bibliography
2012
IEEE J. Solid State Circuits, 2012
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 7th International Workshop on Automation of Software Test, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2006
IEEE J. Solid State Circuits, 2006
2005
A 0.94-ps-RMS-jitter 0.016-mm<sup>2</sup> 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links.
IEEE J. Solid State Circuits, 2005
A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005