Thomas Toifl

According to our database1, Thomas Toifl authored at least 73 papers between 1998 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
F5: Enabling New System Architectures with 2.5D, 3D, and Chiplets.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Session 8 Overview: Ultra-High-Speed Wireline Wireline Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

F6: Optical and Electrical Transceivers for 400GbE and Beyond.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.
IEEE J. Solid State Circuits, 2020

2019
Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018

A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels.
IEEE J. Solid State Circuits, 2018

A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

4×40 Gb/s 2 pJ/bit Optical RX with 8ns Power-on and CDR-Lock Time in 14nm CMOS.
Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2017

28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Adaptive high-speed and ultra-low power optical interconnect for data center communications.
Proceedings of the 2017 19th International Conference on Transparent Optical Networks (ICTON), 2017

Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS.
IEEE J. Solid State Circuits, 2016

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Design considerations on sliding-block viterbi detectors for high-speed data transmission.
Proceedings of the 10th International Conference on Signal Processing and Communication Systems, 2016

A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Design considerations for 50G+ backplane links.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

High-speed link with trellis-coded modulation and Reed-Solomon coding.
Proceedings of the 2016 IEEE Conference on Standards for Communications and Networking, 2016

2015
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth.
IEEE J. Solid State Circuits, 2014

22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm<sup>2</sup> at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os.
Proceedings of the ESSCIRC 2014, 2014

A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI.
Proceedings of the ESSCIRC 2014, 2014

A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm<sup>2</sup> in 32 nm SOI CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS.
IEEE J. Solid State Circuits, 2013

A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS.
IEEE J. Solid State Circuits, 2013

A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS.
IEEE J. Solid State Circuits, 2012

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2012

A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A 28Gb/s source-series terminated TX in 32nm CMOS SOI.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012


2011
A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS.
IEEE J. Solid State Circuits, 2009

LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS.
IEEE J. Solid State Circuits, 2009

2008
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth.
IEEE J. Solid State Circuits, 2008

A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Active compensation of supply noise for a 5-GHz VCO in 45-nm CMOS SOI technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Low-Complexity Adaptive Equalization for High-Speed Chip-to-Chip Communication Paths by Zero-Forcing of Jitter Components.
IEEE Trans. Commun., 2006

A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology.
IEEE J. Solid State Circuits, 2006

A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
A 0.94-ps-RMS-jitter 0.016-mm<sup>2</sup> 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links.
IEEE J. Solid State Circuits, 2005

2000
Integrated circuits for particle physics experiments.
IEEE J. Solid State Circuits, 2000

1999
A radiation-hard 80 MHz phase locked loop for clock and data recovery.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Analysis of parameter-independent PLLs with bang-bang phase-detectors.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998


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