Ming-Yan Tsai

According to our database, Ming-Yan Tsai authored at least 4 papers between 2016 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications.

Ming-Hwa Sheu, Chang-Ming Tsai, Ming-Yan Tsai, Shih-Chang Hsia, S. M. Salahuddin Morsalin, Jin-Fa Lin

Sensors, 2021

2018

An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme.

Ming-Yan Tsai, Po-Yu Kuo, Jin-Fa Lin, Ming-Hwa Sheu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes.

Jin-Fa Lin, Ming-Hwa Sheu, Yin-Tsung Hwang, Chen-Syuan Wong, Ming-Yan Tsai

IEEE Trans. Very Large Scale Integr. Syst., 2017

2016

Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors.

Jin-Fa Lin, Ming-Yan Tsai, Kun-Sheng Li, Yun-Rong Jiang, Yu-Shiang Cheng

J. Low Power Electron., 2016