Jin-Fa Lin

According to our database1, Jin-Fa Lin authored at least 19 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Semantic Lung Segmentation Using Convolutional Neural Networks.
Proceedings of the Bildverarbeitung für die Medizin 2020 - Algorithmen - Systeme, 2020

2019
Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design.
IEICE Trans. Electron., 2019

Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation.
Proceedings of the 2019 International SoC Design Conference, 2019

2018
An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors.
J. Low Power Electron., 2016

MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2014
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2012
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Low power 10-transistor full adder design based on degenerate pass transistor logic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2010
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Low Power Pulse Generator Design Using Hybrid Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2008
Low Complexity Dual-Mode Pulse Generator Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Low Power Multipliers Using Enhenced Row Bypassing Schemes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

2006
A high speed and energy efficient full adder design using complementary & level restoring carry logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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