Ming-Hwa Sheu

IEEE Access, 2023

Fast Measurement of Impedance Calculation for Electrochemical Impedance Spectroscopy.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

Convolutional Neural Network-based Keyword Classification for Mixer Control.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

Heart Valve Disease Recognition Using Phonocardiogram Signal Based on A Lightweight Convolution Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

Unique Feature Extraction and Consistency Network for Skeleton Body Keypoints Configuration and Enhancement.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Knowledge Innovation and Invention, 2023

A Low-Complexity Convolution Network for Upscale Super-Resolution Image.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Knowledge Innovation and Invention, 2023

2022

FHI-Unet: Faster Heterogeneous Images Semantic Segmentation Design and Edge AI Implementation for Visible and Thermal Images Processing.

[BibT_eX]

[DOI]

IEEE Access, 2022

FIBS-Unet: Feature Integration and Block Smoothing Network for Single Image Dehazing.

[BibT_eX]

[DOI]

IEEE Access, 2022

Lightweight Denoising Autoencoder Design for Noise Removal in Electrocardiography.

[BibT_eX]

[DOI]

IEEE Access, 2022

Hardware Accelerator Design of DCT Algorithm With Unique-Group Cosine Coefficients for Mel-Scale Frequency Cepstral Coefficients.

[BibT_eX]

[DOI]

IEEE Access, 2022

Integration Design of Portable ECG Signal Acquisition With Deep-Learning Based Electrode Motion Artifact Removal on an Embedded System.

[BibT_eX]

[DOI]

IEEE Access, 2022

2021

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications.

[BibT_eX]

[DOI]

Sensors, 2021

FGSC: Fuzzy Guided Scale Choice SSD Model for Edge AI Design on Real-Time Vehicle Detection and Class Counting.

[BibT_eX]

[DOI]

Sensors, 2021

Fast-transient high-voltage buck-boost DC-DC conversion with low overshoot.

[BibT_eX]

[DOI]

Shih-Chang Hsia

Jhih-Jian Jhou

Microelectron. J., 2021

Real-time Stereo Television Broadcasting System.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2021

Software and Hardware Integration System Design with Fruit Identification for Smart Electronic Scale Applications.

[BibT_eX]

[DOI]

Wei-Yu Zhu

Wing-Kwong Wong

Szu-Hong Wang

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

Font-End Integrated Circuit Design for Plant Physiological Sensing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

A Novel Bird Detection and Identification based on DPU processor on PYNQ FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

AIoT-based Audio Recognition System for Smart Home Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021

2020

Cost-Effective LED Dimming Driver With Single Chip Design for Smart Lighting System.

[BibT_eX]

[DOI]

Shih-Chang Hsia

Jyun-Jia Ciou

IEEE Access, 2020

Real-Time Lighter Sound Recognition System for IoT Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019

A Fast Non-Overlapping Multi-Camera People Re-Identification Algorithm and Tracking Based on Visual Channel Model.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2019

Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2019

The Image Shape Recovery on Communication Data Lost Damage.

[BibT_eX]

[DOI]

Shih-Chang Hsia

Cheng Hung Hsiao

Proceedings of the Eleventh International Conference on Ubiquitous and Future Networks, 2019

Low-Power Counter-Based Delay Line Design For DPWM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

Implementation of FPGA-based Accelerator for Deep Neural Networks.

[BibT_eX]

[DOI]

Tsung-Han Tsai

Yuan-Chen Ho

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018

An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A new fall detection algorithm based on depth information using RGB-D camera.

[BibT_eX]

[DOI]

Chi-Chia Sun

Yu-Cheng Syu

Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

High-performance reverse converter design for the new four-moduli Set {22n, 2n+1, 2n/2+1, 2n/2-1}.

[BibT_eX]

[DOI]

Siang-Min Siao

Shao-Yu Wang

Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

2016

New adaptable three-moduli set {2n+k, 2n - 1, 2n-1 - 1} for residue number system-based finite impulse response implementation.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

Single image fog removal algorithm based on an improved dark channel prior method.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016

Object detection using adaptive block-based background model.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2016

Intelligent system design for variable color temperature LED street light.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2016

Edge-based moving object tracking algorithm for an embedded system.

[BibT_eX]

[DOI]

Kai Xiang Yang

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

High efficient hardware allocation framework of arbitrary inverse transform coding blocks in H.265.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

Efficient object motion detection based on RGB-D image.

[BibT_eX]

[DOI]

Yi-Hua Wang

Chi-Chia Sun

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015

Extendable multi-pixel object labeling for digital image.

[BibT_eX]

[DOI]

Shyue-Wen Yang

Tzu-Hsiung Chen

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015

2014

High Dynamic Range Image Based on Block-Based Edge Strength for Embedded System Design.

[BibT_eX]

[DOI]

Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014

Ultra Low Power Circuit Design Based on Adiabatic Logic.

[BibT_eX]

[DOI]

Chi-Chia Sun

Cheng Chih Wang

Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014

Feature Points Based Video Object Tracking for Dynamic Scenes and Its FPGA System Prototyping.

[BibT_eX]

[DOI]

Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014

2013

Efficient Reverse Converter Design for New Adaptable Four-Moduli Set {2n + k, 2n + 1, 2n - 1, 22n + 1}.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Fast Image Blending and Deghosting for Panoramic Video.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2013

A Computation Efficiency AND-CFAR for FMCW Radar Receiver.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2013

2012

Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Block-Based Major Color Method for Foreground Object Detection on Embedded SoC Platforms.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2012

A hybrid pixel-based background model for image foreground object detection in complex sence.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Telecommunications and Signal Processing, 2012

A robust background modeling and foreground object detection using color component analysis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2012

Fast image moving object segmentation based on block texture for embedded system implementation.

[BibT_eX]

[DOI]

Shyue-Wen Yang

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

Low power 10-transistor full adder design based on degenerate pass transistor logic.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Region-Based Background Subtraction for Complex Sense on Embedded Platforms.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2012

2011

New Reverse Converter Design of Moduli Set {2n, 2n+1-1, 2n-1}.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on Innovations in Bio-inspired Computing and Applications, 2011

Efficient Color-Ingredient Particle Filter for Video Object Tracking.

[BibT_eX]

[DOI]

Proceedings of the Second International Conference on Innovations in Bio-inspired Computing and Applications, 2011

2010

Fast First-Order Polynomials Convolution Interpolation for Real-Time Digital Image Reconstruction.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2010

An Efficient Architecture of Extended Linear Interpolation for Image Processing.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2010

A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Low Power Pulse Generator Design Using Hybrid Logic.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Efficient Multi-Layer Background Model on Complex Environment for Foreground Object Detection.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2010), 2010

Fast Texture-Based Object Tracking Algorithm on Embedded Platform.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Frontier of Computer Science and Technology, 2010

FPGA implementation for image object detection system on NoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Efficient VLSI Design of a Reverse RNS Converter for New Flexible 4-Moduli Set (2p+k, 2p+1, 2p-1, 22p+1).

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Image Object Detection and Tracking Implementation for Outdoor Scenes on an Embedded Soc Platform.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2009), 2009

Parallel 3-Pixel Labeling Method and its Hardware Architecture Design.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Information Assurance and Security, 2009

2008

VLSI Design of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2008

High-performance very large scale integration architecture design for various-ratio image scaling.

[BibT_eX]

[DOI]

J. Electronic Imaging, 2008

Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1).

[BibT_eX]

[DOI]

Chao-Hsiang Wang

IEICE Trans. Inf. Syst., 2008

Area-Time Efficient Modulo 2n - 1 Adder Design Using Hybrid Carry Selection.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2008

Low Complexity Dual-Mode Pulse Generator Designs.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

An efficient convolution interpolation kernel for digital image scaling.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2008

The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Software and Systems, 2008

Real-time FPGA architecture of extended linear convolution for digital image scaling.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n, 2n+1-1, 2n-1).

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Low Power Multipliers Using Enhenced Row Bypassing Schemes.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Fast Fair Crossbar Scheduler for On-chip Router.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

The VLSI Design of Winscale for Digital Image Scaling.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007), 2007

2006

Automatic Generation of Programmable Parallel CRC & Scrambler Designs.

[BibT_eX]

[DOI]

Jiun-Yan Chen

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

The VLSI design of de-interlacing with scene change detection.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A high speed and energy efficient full adder design using complementary & level restoring carry logic.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Film-to-Video Conversion with Scene Cut Detection.

[BibT_eX]

[DOI]

Proceedings of the First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August, 2006

Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1).

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection.

[BibT_eX]

[DOI]

Proceedings of the Advances in Multimedia Information Processing, 2005

VLSI architecture design for a fast parallel label assignment in binary image.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Directional interpolation for field-sequential stereoscopic video.

[BibT_eX]

[DOI]

Hsien-Huang P. Wu

Tung-Yu Yang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

An efficient VLSI design for a residue to binary converter for general balance moduli (2n-3, 2n+1, 2n-1, 2n+3).

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2004

2003

A Fast Additive Normalization Method for Exponential Computation.

[BibT_eX]

[DOI]

Chichyang Chen

Rui-Lin Chen

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002

Fast compensative design approach for the approximate squaring function.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2002

Fast design approach for implementing the approximate squaring function.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001

A Systematic Approach for Parallel CRC Computations.

[BibT_eX]

[DOI]

J. Inf. Sci. Eng., 2001

VLSI architecture of extended in-place path metric update for Viterbi decoders.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

An efficient approach for in-place scheduling of path metric update in Viterbi decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

High-speed generation of LFSR signatures.

[BibT_eX]

[DOI]

Ming-Der Shieh

Hsin-Fu Lo