Yin-Tsung Hwang
Orcid: 0000-0001-9233-0477
According to our database1,
Yin-Tsung Hwang
authored at least 82 papers
between 1992 and 2023.
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Bibliography
2023
Efficient Image Aided Odometry Estimation Scheme for LiDAR Camera based SLAM Systems.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023
2022
Acceleration Study of Two-Stage and Deep-Learning Based Facial Direction Detection on GPU-Based Edge Device.
Proceedings of the 4th IEEE Global Conference on Life Sciences and Technologies, 2022
Proceedings of the IEEE International Conference on Consumer Electronics, 2022
Quantized Lite Convolutional Neural Network Hardware Accelerator Design with FPGA for Face Direction Recognition.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022
2021
Fixed-Complexity Tree Search Schemes for Detecting Generalized Spatially Modulated Signals: Algorithms and Hardware Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Iris Location and Recognition by Deep-Learning Networks Based Design for Biometric Authorization.
Proceedings of the 3rd IEEE Global Conference on Life Sciences and Technologies, 2021
Sensor Data Fusion of Intelligent Autonomous Mover for Object Detection and Collision Avoidance in Environments with Surrounding Crowds.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021
Ultrasound Phased Array Radar Design for Ranging and Direction of Arrival Estimation.
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
Effective Two-Stage Processing Based Lite Deep Learning Classifier for Gender Detection.
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2021
iAMEC, an Intelligent Autonomous Mover for Navigation in Indoor People Rich Environments.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Design and Chip Implementation of a SMI/MVDR Dual-Mode Beamformer for Wireless MIMO Communication Systems.
IEEE Access, 2020
High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator.
Proceedings of the International SoC Design Conference, 2020
2019
A Low-Complexity Maximum Likelihood Detector for the Spatially Modulated Signals: Algorithm and Hardware Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
The IEEE International Conference on Consumer Electronics-Taiwan 2018 [Conference Reports].
IEEE Consumer Electron. Mag., 2019
VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems.
IEEE Access, 2019
Proceedings of the 2019 International SoC Design Conference, 2019
A High-Performance Pedestrian Detector and Its Implementation on Embedded Systems for Hypermarket Environment.
Proceedings of the 2019 International SoC Design Conference, 2019
Deep-Learning Based Pedestrian Direction Detection for Anti-collision of Intelligent Self-propelled Vehicles.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2017
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Development of a high throughput image compression system for optical remote sensing.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017
2016
New adaptable three-moduli set {2<i><sup>n</sup></i><sup>+</sup><i><sup>k</sup></i>, 2<i><sup>n</sup></i> - 1, 2<i><sup>n</sup></i><sup>-1</sup> - 1} for residue number system-based finite impulse response implementation.
IEICE Electron. Express, 2016
An efficient motion blurred image restoration scheme based on frequency domain estimation.
Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan, 2016
MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Editorial: Signal Processing for Communication/Biomedical Systems and Reliability Improvement.
J. Signal Process. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
A Low-Complexity Embedded Compression Codec Design With Rate Control for High-Definition Video.
IEEE Trans. Circuits Syst. Video Technol., 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Efficient block adaptive point spread function estimation and out-of-focus image restoration scheme.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2015
2014
A Low Complexity Geometric Mean Decomposition Computing Scheme and Its High Throughput VLSI Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Feature Points Based Video Object Tracking for Dynamic Scenes and Its FPGA System Prototyping.
Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014
2013
A Constant Throughput Geometric Mean Decomposition Scheme Design for Wireless MIMO Precoding.
IEEE Trans. Veh. Technol., 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
2012
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2012
J. Electr. Comput. Eng., 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Efficient TWIN-VQ audio decoder implementation on a configurable processor using instruction extension.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012
2011
Lossless Compression of Hyperspectral Images Using Adaptive Prediction and Backward Search Schemes.
J. Inf. Sci. Eng., 2011
Design and implementation of a high-throughput fully parallel complex-valued QR factorisation chips.
IET Circuits Devices Syst., 2011
IEEE Embed. Syst. Lett., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
An Efficient Lossless Compression Scheme for Hyperspectral Images Using Two-Stage Prediction.
IEEE Geosci. Remote. Sens. Lett., 2010
A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
MMSE-QR factorization systolic array design for applications in MIMO signal detections.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Lossless Coding of Multiband Images Using Interband Data Correlation and Error Feedback Prediction Scheme.
Proceedings of the Sixth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2010), 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
Proceedings of IEEE International Conference on Communications, 2009
Automatic IP Interface Synthesis Supporting Multi-layer Communication Protocols in SoC Designs.
Proceedings of the Fifth International Conference on Information Assurance and Security, 2009
2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
A low complexity complex QR factorization design for signal detection in MIMO OFDM systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Conference on Embedded Software and Systems, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Wavelet Based Lossless Video Compression Using Motion Compensated Temporal Filtering.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
A high speed and energy efficient full adder design using complementary & level restoring carry logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).
IEEE Trans. Computers, 2004
VLSI architecture exploration for sliding-window Log-MAP decoders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
An area-efficient systolic division circuit over GF(2<sup>m</sup>) for secure communication.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
A rapid prototyping embedded system platform and its HW/SW communication interface generation and verification.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
1998
J. Inf. Sci. Eng., 1998
J. Inf. Sci. Eng., 1998
Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System.
Proceedings of the 11th International Symposium on System Synthesis, 1998
1996
Proceedings of the 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), 1996
1995
A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays.
J. VLSI Signal Process., 1995
1992
Proceedings of the Application Specific Array Processors, 1992