Yin-Tsung Hwang

According to our database1, Yin-Tsung Hwang authored at least 68 papers between 1992 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Design and Chip Implementation of a SMI/MVDR Dual-Mode Beamformer for Wireless MIMO Communication Systems.
IEEE Access, 2020

2019
A Low-Complexity Maximum Likelihood Detector for the Spatially Modulated Signals: Algorithm and Hardware Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

The IEEE International Conference on Consumer Electronics-Taiwan 2018 [Conference Reports].
IEEE Consumer Electron. Mag., 2019

VLSI Design of a High Throughput Hybrid Precoding Processor for Wireless MIMO Systems.
IEEE Access, 2019

Projection Matching Pursuit based DoA Estimation Scheme and its FPGA Implementation.
Proceedings of the 2019 International SoC Design Conference, 2019

A High-Performance Pedestrian Detector and Its Implementation on Embedded Systems for Hypermarket Environment.
Proceedings of the 2019 International SoC Design Conference, 2019

Deep-Learning Based Pedestrian Direction Detection for Anti-collision of Intelligent Self-propelled Vehicles.
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

An Enhanced MUSIC DoA Scanning Scheme for Array Radar Sensing in Autonomous Movers.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2017
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Development of a high throughput image compression system for optical remote sensing.
Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

2016
New adaptable three-moduli set {2<i><sup>n</sup></i><sup>+</sup><i><sup>k</sup></i>, 2<i><sup>n</sup></i> - 1, 2<i><sup>n</sup></i><sup>-1</sup> - 1} for residue number system-based finite impulse response implementation.
IEICE Electron. Express, 2016

MVDR based adaptive beamformer design and its FPGA implementation for ultrasonic imaging.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Editorial: Signal Processing for Communication/Biomedical Systems and Reliability Improvement.
J. Signal Process. Syst., 2015

Low-Complexity High-Throughput QR Decomposition Design for MIMO Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Low-Complexity Embedded Compression Codec Design With Rate Control for High-Definition Video.
IEEE Trans. Circuits Syst. Video Technol., 2015

A high throughput unified SVD/QRD precoder design for MIMO OFDM systems.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

2014
A Low Complexity Geometric Mean Decomposition Computing Scheme and Its High Throughput VLSI Implementation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An IP interface design compiler with SystemC based input specifications.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Feature Points Based Video Object Tracking for Dynamic Scenes and Its FPGA System Prototyping.
Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014

2013
A Constant Throughput Geometric Mean Decomposition Scheme Design for Wireless MIMO Precoding.
IEEE Trans. Veh. Technol., 2013

Design and implementation of a high throughput soft output MIMO detector.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

2012
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Implementations of Signal-Processing Algorithms for OFDM Systems.
J. Electr. Comput. Eng., 2012

Design and implementation of an optical OFDM baseband receiver in FPGA.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Low power 10-transistor full adder design based on degenerate pass transistor logic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An efficient QR decomposition design for MIMO systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Efficient TWIN-VQ audio decoder implementation on a configurable processor using instruction extension.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Design and FPGA implementation of a FMCW radar baseband processor.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Lossless Compression of Hyperspectral Images Using Adaptive Prediction and Backward Search Schemes.
J. Inf. Sci. Eng., 2011

Design and implementation of a high-throughput fully parallel complex-valued QR factorisation chips.
IET Circuits Devices Syst., 2011

Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign.
IEEE Embed. Syst. Lett., 2011

Low complexity baseband transceiver design for narrow band power line communication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
An Efficient Lossless Compression Scheme for Hyperspectral Images Using Two-Stage Prediction.
IEEE Geosci. Remote. Sens. Lett., 2010

A Low Complexity Dual-Mode Pulse-Triggered Flip-Flop Design Based on Unified AND/XNOR Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Low Power Pulse Generator Design Using Hybrid Logic.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

MMSE-QR factorization systolic array design for applications in MIMO signal detections.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Lossless Coding of Multiband Images Using Interband Data Correlation and Error Feedback Prediction Scheme.
Proceedings of the Sixth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2010), 2010

Design and implementation of a low complexity lossless video codec.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Space-Frequency-Coded MIMO OFDM Receivers Based on Gaussian Message Passing.
Proceedings of IEEE International Conference on Communications, 2009

Automatic IP Interface Synthesis Supporting Multi-layer Communication Protocols in SoC Designs.
Proceedings of the Fifth International Conference on Information Assurance and Security, 2009

2008
Low Complexity Dual-Mode Pulse Generator Designs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A low complexity complex QR factorization design for signal detection in MIMO OFDM systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

HW/SW Auto-Coupling for Fast IP Integration in SoC Designs.
Proceedings of the International Conference on Embedded Software and Systems, 2008

2007
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Wavelet Based Lossless Video Compression Using Motion Compensated Temporal Filtering.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Low Power Multipliers Using Enhenced Row Bypassing Schemes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

2006
Automatic Generation of Programmable Parallel CRC & Scrambler Designs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A high speed and energy efficient full adder design using complementary & level restoring carry logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2005

The embedded software consortium of taiwan.
ACM Trans. Embed. Comput. Syst., 2005

Block-wise adaptive modulation for OFDM WLAN systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).
IEEE Trans. Computers, 2004

VLSI architecture exploration for sliding-window Log-MAP decoders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
FPGA realization of an OFDM frame synchronization design for dispersive channels.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
An area-efficient systolic division circuit over GF(2/sup m/) for secure communication.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A rapid prototyping embedded system platform and its HW/SW communication interface generation and verification.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Design and implementation of channel equalizers for block transmission systems.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1998
Rapid Prototyping of Hardware / Software Codesign for Embedded Signal Processing.
J. Inf. Sci. Eng., 1998

Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors.
J. Inf. Sci. Eng., 1998

Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System.
Proceedings of the 11th International Symposium on System Synthesis, 1998

1996
Distributed arithmetic-based architectures for high speed IIR filter design.
Proceedings of the 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), 1996

1995
A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays.
J. VLSI Signal Process., 1995

1992
MSSM - A design aid for multi-stage systolic mapping.
J. VLSI Signal Process., 1992

On systolic mapping of multi-stage algorithms.
Proceedings of the Application Specific Array Processors, 1992


  Loading...