Ming-Yu Tsai
According to our database1,
Ming-Yu Tsai
authored at least 16 papers
between 2002 and 2023.
Collaborative distances:
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Bibliography
2023
Proceedings of the 8th IEEE/ACIS International Conference on Big Data, 2023
2015
A Virtual Cluster Head Election Scheme for Energy-Efficient Routing in Wireless Sensor Networks.
Proceedings of the 3rd International Conference on Future Internet of Things and Cloud, 2015
2010
Improved Area-Efficient Weighted Modulo 2<sup>n</sup> + 1 Adder Design With Simple Correction Schemes.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
2009
Corrections to "VLSI Design of Diminished-One Modulo 2<sup>n</sup> + 1 Adder Using Circular Carry Selection" [Sep 08 897-901].
IEEE Trans. Circuits Syst. II Express Briefs, 2009
2008
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2006
Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition.
IEICE Trans. Inf. Syst., 2005
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 IEEE International Conference on e-Technology, e-Commerce, and e-Services (EEE 2005), 29 March, 2005
2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Automatic Integration of Inter-Enterprise Processes with Hierarchical Broker Framework.
Proceedings of the ICEIS 2004, 2004
2002
Partition methodology for the final adder in a tree-structure parallel multiplier generator.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002